Dual-Modal Memory Interface Controller Bandwidth Adaptation
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Solution Overview
Problem
In computing systems with heterogeneous processors, data transfer bottlenecks occur due to varying data transport needs, leading to underutilization and power wastage, as existing solutions do not effectively optimize bus connections for different processor architectures.
Innovation Solution
A dual-modal memory interface controller that switches between narrow-band and wide-band modes, providing differently-graded bandwidth capacities to processors, allowing virtualization of system memory units and enabling efficient data transfer through virtual I/O interfaces, thereby optimizing bus utilization and preventing bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bandwidth capacity for data buses is maximized to prevent bottlenecks, then data transfer capability is improved, but power consumption increases due to underutilization and idleness in bus connections
Solution Approach 1:
The memory interface controller dynamically switches between wide-band mode and narrow-band mode based on the data throughput requirements of different processors. This dynamic adjustment allows the system to optimize bandwidth capacity for high-performance processors while reducing power consumption for processors with lower data transfer needs, resolving the contradiction between maximizing data transfer capability and minimizing power consumption
Solution Approach 2:
The system changes the bandwidth parameter of the memory interface controller according to different processor types. By configuring the controller to operate in wide-band mode for processors requiring high data throughput and narrow-band mode for processors with lower requirements, the system adapts bandwidth capacity to match actual needs, preventing both bottlenecks and power wastage
2Productivity
If a single high-bandwidth memory interface is provided for all processors, then data transfer bottleneck is prevented, but bus utilization efficiency decreases due to underutilization by processors with small data throughput rates
Solution Approach 1:
Different portions of the system (memory interface controller modes) are assigned different bandwidth characteristics tailored to specific processor needs. High-performance processors receive wide-band mode interfaces with high throughput capacity, while other processors receive narrow-band mode interfaces with lower capacity, ensuring each processor type operates at optimal efficiency without over-provisioning
Solution Approach 2:
The memory interface controller is designed to perform multiple functions by switching between wide-band and narrow-band modes. This multi-functionality allows a single controller to serve diverse processor types with varying bandwidth requirements, improving overall system adaptability and bus utilization efficiency
Data Source
AI summary
A dual-model memory interface of a computing system is provided, configurable to present memory interfaces having differently-graded bandwidth capacity to different processors of the computing system. A mode switch controller of the memory interface controller, based on at least an arbitration rule written to a configuration register, switches the memory interface controller between a narrow-band mode and a wide-band mode. In each mode, the memory interface controller disables either a plurality of narrow-band memory interfaces of the memory interface controller according to a first bus standard, or a wide-band memory interface of the memory interface controller according to a second bus standard. The memory interface controller virtualizes a plurality of system memory units of the computing system as a virtual wide-band memory unit according to the second bus standard, or virtualizes a system memory unit of the computing system as a virtual narrow-band memory unit according to the first bus standard.