Dual-Mode ASIC Tile Operation for Power and Current Constraints
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Solution Overview
Problem
Existing neural network computation systems face challenges in managing power consumption and current rate changes during high computational loads, which can exceed design constraints and make them vulnerable to attacks.
Innovation Solution
Integrated circuits, such as ASICs, are designed to operate in two modes: a first mode where all tiles process data concurrently and a second mode where a delay is introduced to stagger data processing, allowing for dynamic selection based on the number of operable tiles or columns, thereby controlling power consumption and current changes within design constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all tiles process data concurrently in the first mode, then computational productivity is improved, but power consumption and current rate changes exceed design constraints
Solution Approach 1:
The system dynamically switches between two operational modes based on computational load. In the first mode, all tiles operate concurrently to maximize throughput when power constraints are not violated. In the second mode, tiles are staggered in time to reduce instantaneous power consumption when constraints are exceeded. This dynamic adaptation resolves the contradiction by adjusting the degree of parallelism according to real-time power conditions.
Solution Approach 2:
The second mode implements periodic action by dividing tile operations into sequential time slots rather than simultaneous execution. Tiles are activated in staggered periods, with each tile receiving input data at different clock cycles. This periodic activation pattern reduces the instantaneous power consumption and current rate changes while still achieving the required computational throughput over time.
2Speed
If all tiles process data concurrently, then computational speed is improved, but the system becomes vulnerable to attacks by exceeding current rate constraints
Solution Approach 1:
The system dynamically adjusts its operational mode based on the number of operable tiles and computational load. When the count of operable tiles exceeds a threshold, the system transitions to the second mode with staggered tile activation. This dynamic response prevents attack scenarios where simultaneous activation of all tiles could be exploited, while maintaining high speed operation during normal conditions.
3Use of energy by moving object
If delay registers are introduced to stagger tile operation, then power consumption is controlled within constraints, but computational productivity decreases
Solution Approach 1:
The system dynamically selects between full parallelism (first mode) and staggered operation (second mode) based on whether power constraints are violated. This dynamic mode selection ensures that the delay-induced productivity loss only occurs when absolutely necessary for power control, maximizing overall system efficiency.
Solution Approach 2:
The second mode maintains continuous useful action by ensuring that while tiles are staggered in time, the overall computational pipeline remains active. Input data is continuously supplied to tiles as they become available, and output data flows continuously from completed tiles. This continuous flow minimizes idle time and maintains high utilization of the computational resources despite the staggered activation pattern.
Data Source
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Figure 2B
AI summary
A method for operating an integrated circuit chip including multiple tiles (202a-202d) includes determining a configuration for the tiles for execution of a computation. When the configuration for the tiles satisfies a first criterion, the integrated circuit is operated in a first mode, including concurrently receiving respective input data (208a, 208b) at each of the tiles (202a-202d). When the configuration for the tiles satisfies a second criterion, the integrated circuit is operated in a second mode, including: at a first time, concurrently receiving respective first input data (208a, 208b) at each tile (202a, 202b) of a first group of tiles; at the first time, storing respective second input data (208a, 208b) in each of multiple delay registers (212a, 212b), each delay register corresponding to a tile (202c, 202d) of a second group of tiles; at a second time, releasing the second input data from the delay registers (212a, 212b) and receiving the released respective second input data at each tile (202c, 202d) of the second group of tiles.