Dual-Mode Chiplet Interface for AIB and UCIe Interoperability
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Solution Overview
Problem
The integration of multiple chiplets with different interfaces in a single multichip package leads to compatibility issues such as routing congestion, signal performance degradation, and channel mismatch due to lack of standardized connections, particularly between Advanced Interconnect Bus (AIB) and Universal Chiplet Interconnect Express (UCIe) interfaces.
Innovation Solution
A dual-mode chiplet with adaptable bump map assignments and a modularized AIB design are implemented to enable interoperability between AIB and UCIe interfaces, allowing for flexible signal orientation and channel configurations, thereby reducing compatibility issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chiplets with different interfaces (AIB and UCIe) are integrated in a single multichip package, then functionality and cost are improved, but interface compatibility issues arise including routing congestion, signal performance degradation, and channel mismatch
Solution Approach 1:
The patent implements a universal interface layer that can operate in multiple modes (AIB mode and UCIe mode) to interface with different chiplet types. The interface includes mode selection logic and configurable signal routing that allows a single interface design to accommodate both AIB and UCIe standards, eliminating the need for separate dedicated interfaces for each chiplet type.
Solution Approach 2:
The patent introduces an intermediary interface layer between the core logic and the chiplets that acts as a translator or adapter. This intermediary layer handles the protocol conversion and signal mapping between different interface standards (AIB and UCIe), resolving compatibility issues without requiring changes to the core logic or the chiplets themselves.
2Manufacturing precision
If proprietary chiplet interconnects are used without standardization, then specific performance requirements can be met, but routing congestion and signal performance issues occur
Solution Approach 1:
The patent segments the interface into distinct functional blocks: mode selection logic, signal routing switches, and protocol translation layers. This segmentation allows each component to be optimized independently for its specific function while maintaining overall system coherence, reducing routing complexity through modular design.
Solution Approach 2:
The patent implements dynamic signal routing where the interface can reconfigure its connection paths based on the detected chiplet type and mode. The routing switches can dynamically change their configuration to optimize signal paths for either AIB or UCIe protocols, adapting to different performance requirements without fixed rigid routing.
3Ease of manufacture
If fixed bump map assignments are used for chiplet interfaces, then manufacturing simplicity is maintained, but adaptability to different interface standards is reduced
Solution Approach 1:
The patent employs parameter-configurable bump map assignments where the interface can change its operational parameters (such as signal mapping, timing, and voltage levels) based on the detected interface standard. The same physical bump map can be reconfigured through parameter changes to support either AIB or UCIe protocols, maintaining manufacturing simplicity while achieving versatility.
Data Source
AI summary
The present disclosure is directed to improving compatibility between chiplets integrated with disparate chiplet interfaces. To reduce compatibility issues due non-matching bump maps, a dual-mode bump map assignment may be implemented to enable a chiplet to utilize multiple signal number sequence assignments. Additionally, a modularized Advanced Interface Bus (AIB) interface may be implemented to reduce channel mismatch in AIB -UCIe multi-channel interoperability.