Dual-Mode Clock Generating Circuit for Low Latency and Jitter Suppression
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Solution Overview
Problem
Conventional Serializer/Deserializer (SerDes) physical layer circuits face challenges in designing a low pass filter that meets the different requirements of analog clock data recovery (ACDR) and clock multiplication unit (CMU) modes, leading to increased jitter in the CMU's output clock due to conflicting capacitance needs and switch resistor interference.
Innovation Solution
A clock generating circuit with a filter and ring oscillator configuration that determines separate voltage signals for ACDR and CMU modes, using a switch and capacitor in series to isolate the voltage signals, allowing the ring oscillator to output clocks without interference, and a hybrid circuit with a multiplexer to selectively connect phase detectors and charge pumps based on operation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the capacitance of capacitor 140 is made small to reduce loop latency in ACDR mode, then loop latency is reduced, but reference jitter suppression capability deteriorates in CMU mode
Solution Approach 1:
The patent applies dynamics by making the capacitor 140 dynamically configurable through switch 130. The capacitance value can be changed between small (switch off) and large (switch on) states, allowing the low pass filter to adapt to different operational modes (ACDR vs CMU) and resolve the contradiction between loop latency and jitter suppression requirements
2Reliability
If the capacitance of capacitor 140 is made large to suppress reference jitter in CMU mode, then reference jitter suppression is improved, but loop latency increases in ACDR mode
Solution Approach 1:
The patent uses dynamics by enabling the capacitor 140 to be dynamically switched between connected and disconnected states. When switch 130 is on, the large capacitance suppresses reference jitter in CMU mode; when switch 130 is off, the small capacitance reduces loop latency in ACDR mode, thus resolving the contradiction
3Reliability
If switch 130 is turned on to enable capacitor 140 for CMU mode, then reference jitter suppression is improved, but switch resistor interference and gate voltage interference worsen
Solution Approach 1:
The patent applies dynamics by controlling the switch 130 state based on operational mode. The switch is only turned on when CMU mode is active and reference jitter suppression is needed, and turned off when ACDR mode is active to avoid the harmful effects of switch resistor and gate voltage interference
Solution Approach 2:
The patent uses periodic action by selectively activating the switch 130 only during CMU operation periods when jitter suppression is required, and deactivating it during ACDR operation periods, thus achieving beneficial effects only when needed and avoiding harmful effects when not needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces loop latency in ACDR mode and deeply suppresses reference jitter with proper loop stability and bandwidth in CMU mode, effectively addressing the design dilemma of the low pass filter.
Implementation Method 1
a second filtering circuit, coupled between the first node and the reference voltage terminal and connected with the first filtering circuit in parallel, including a switch and a capacitor connected in series
Implementation Method 2
the switch is turned off in the ACDR mode and turned on in the CMU mode
Data Source
AI summary
Disclosed is a clock generating circuit capable of operating in an analog clock data recovery (ACDR) mode to reduce the loop latency or a clock multiplication unit (CMU) mode to suppress reference jitter. The circuit includes a filter and an oscillator. The filter receives an input signal to determine voltages of a first node and a second node respectively and includes a first filtering circuit and a second filtering circuit coupled in parallel between the first node and a reference voltage terminal. The second filtering circuit includes a switch and a capacitor connected in series, wherein the second node is between the switch and capacitor, and the switch is turned off in the ACDR mode and turned on in the CMU mode. The oscillator outputs a clock according to the first node's voltage in the ACDR mode or according to the second node's voltage in the CMU mode.