Dual-Mode CMOS Cell Logic for Sub-Leakage Energy Harvesting
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Solution Overview
Problem
Conventional miniaturized sensor nodes are unable to operate in the sub-leakage regime, making them unsuitable for purely harvested operation, and existing solutions either require high performance at the cost of energy efficiency or reduce leakage current at the expense of speed and area, while battery-indifferent systems need to manage fluctuating power efficiently.
Innovation Solution
A dual-mode logic structure and ripple power gating self-startup scheme for CMOS gate circuits, allowing operation in both normal and leakage suppression modes, with NMOS headers and PMOS footers that can cut off leakage paths, enabling efficient energy use and cold start-up with limited harvested power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional miniaturized sensor nodes use standard CMOS circuits, then they achieve acceptable speed and performance, but they cannot operate in the sub-leakage regime and are unsuitable for purely harvested operation
Solution Approach 1:
The patent implements dynamic operation modes that allow the sensor node to switch between battery-powered mode and purely harvested mode. In purely harvested mode, the system dynamically adjusts its operation to function in the sub-leakage regime by enabling leakage suppression circuits and adjusting power management parameters in real-time based on available harvested energy
Solution Approach 2:
The system changes operational parameters including voltage levels, current thresholds, and power management settings to enable sub-leakage operation. The power management circuit adjusts these parameters dynamically to match the available harvested power, allowing the node to operate with extremely low power consumption when battery is unavailable
2Loss of energy
If separate header and footer transistors are added to reduce leakage in custom standard cells, then leakage current is reduced, but 8 additional transistors are required in each standard cell resulting in larger area
Solution Approach 1:
The patent introduces universal header and footer circuits that can be applied to any standard cell type (logic gates, flip-flops, etc.) to suppress leakage current. These universal circuits provide a standardized approach that reduces leakage across the entire design without requiring custom modifications to each individual cell, optimizing the area-leakage tradeoff through reuse of the same leakage suppression mechanism
Solution Approach 2:
The leakage suppression is applied locally at the header and footer of each standard cell, targeting specifically the leakage paths without modifying the core logic functionality. This localized approach allows leakage reduction while minimizing impact on the main cell area and functionality
3Loss of energy
If header and footer transistors are integrated to reduce leakage current, then leakage current is reduced, but the speed of the custom standard cells is heavily degraded
Solution Approach 1:
The header and footer circuits are designed to be dynamically controllable, switching between active leakage suppression mode and high-speed mode. During normal operation when battery power is available, the circuits operate in high-speed mode with minimal leakage suppression. When transitioning to purely harvested mode, they activate full leakage suppression, allowing the system to optimize between speed and leakage reduction based on power availability
Solution Approach 2:
The circuit parameters including transistor sizing, threshold voltages, and control signal levels are optimized to balance leakage suppression and speed performance. By carefully tuning these parameters, the patent achieves effective leakage reduction while minimizing the negative impact on switching speed and signal propagation delay
4Use of energy by moving object
If battery-indifferent operation is implemented to achieve sub-nW power when battery is out of energy, then power consumption is reduced to fit fluctuating harvested power, but the system must handle complex power management and mode switching
Solution Approach 1:
The power management system incorporates self-adjusting mechanisms that automatically respond to changes in harvested power availability. The circuits monitor voltage levels and power conditions, and autonomously switch between operation modes or adjust parameters without requiring complex external control logic, reducing the overall system complexity while maintaining battery-indifferent operation
Solution Approach 2:
The system uses feedback mechanisms to monitor power availability and adjust operation accordingly. Power management circuits continuously monitor the state of the battery and harvested power source, and use this feedback to control mode switching and parameter adjustment, enabling adaptive power management that handles complexity through closed-loop control rather than open-loop complexity
Data Source
AI summary
A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system. The cell gate structure comprises a CMOS gate circuit; a header circuit coupled to the CMOS gate circuit and comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit; and a footer circuit coupled to the CMOS gate circuit and comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage; wherein the header and footer circuits are configured for switching between different operation modes of the multi-mode system, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled.