Shared-Back-End Dual-Mode Comparator for Low-Power ATE
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Solution Overview
Problem
Existing dual mode comparators in automatic testing equipment require separate circuitry for each mode and multiple gain stages, leading to high power consumption and silicon area usage, which limits their efficiency and scalability.
Innovation Solution
A dual mode comparator circuit utilizing differential transistor pairs and a shared comparator back end with a multiplexor to select and amplify input signals, reducing the number of gain stages and power consumption while maintaining performance by operating in the current domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuitry is provided for each comparator mode, then mode-specific performance is optimized, but device complexity and silicon area increase
Solution Approach 1:
The patent implements a single comparator back end that can handle multiple comparator modes (differential mode, common mode, and single-ended mode) through a multiplexor that routes signals appropriately. This universal back end eliminates the need for separate circuitry for each mode while maintaining the ability to perform all required comparison functions.
Solution Approach 2:
The patent merges multiple comparator modes into a single integrated circuit by combining the differential transistor pairs with a shared back end. The multiplexor combines the routing function to direct signals from different transistor pairs to the common back end, reducing overall circuit complexity while preserving mode-specific performance characteristics.
2Measurement precision
If multiple gain stages are used, then comparison precision is improved, but power consumption increases
Solution Approach 1:
The patent uses a single gain stage in the comparator back end rather than multiple stages, providing sufficient amplification for the application requirements without the excessive power consumption of additional stages. This partial action approach achieves the necessary precision while minimizing power usage.
Solution Approach 2:
The patent optimizes the gain stage parameters to achieve the required comparison precision with a single stage. By carefully selecting transistor sizes, bias currents, and feedback configurations, the design achieves adequate amplification without requiring multiple power-consuming stages.
3Measurement precision
If multiple gain stages are used, then comparison precision is improved, but silicon area increases
Solution Approach 1:
The patent combines multiple comparator modes and their associated gain stages into a single shared back end, significantly reducing the total silicon area required. The multiplexor enables this consolidation by routing signals from different transistor pairs to the common back end, eliminating redundant circuitry.
Solution Approach 2:
The universal comparator back end serves multiple comparator modes with a single gain stage, reducing the silicon area that would otherwise be required for separate gain stages in each mode. This multi-functional design achieves the necessary precision while minimizing area consumption.
Data Source
AI summary
A dual mode comparator circuit is disclosed. The dual mode comparator includes a plurality of differential transistor pairs. Each differential transistor pair includes a plurality of inputs and outputs. The outputs of the differential transistor pairs are coupled to inputs of a multiplexor. The multiplexor includes at least one control input for selecting between the multiplexor inputs and provides the selected input to the multiplexor output. The dual mode comparator further includes a comparator back end that is coupled to the output of the multiplexor. The comparator back end may include a folded cascode and additional gain stages. The comparator back end provides the comparator output to the next stage. The dual mode comparator may be used in automatic testing equipment embodiments.