Dual-Mode Counter Module for Network Traffic Metering

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Solution Overview

Problem

Communication network devices face bottlenecks in counting network traffic events due to slow counter memory update rates, especially when event rates exceed the maximum update rate, leading to inaccuracies in real-time counting.

Innovation Solution

A dual-mode counter module that switches between statistical and deterministic sampling based on traffic load conditions, using a load determination circuit to assess packet traffic load and adjust counting modes, and a meter module with a conformance unit and token bucket memory to manage packet traffic rates, allowing for efficient counting and metering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If statistical estimation techniques are used to reduce memory update rates, then memory space/area is reduced and update rate requirements are lowered, but measurement precision deteriorates because exact counting is not provided

Engineering Contradiction:
Improvememory spaceVSAvoidcounting accuracy
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The system dynamically switches between statistical estimation mode and deterministic counting mode based on real-time traffic load conditions. When traffic load is high, statistical estimation is used to reduce memory update requirements. When traffic load is low, deterministic counting is used to provide exact counts. This dynamic adaptation resolves the contradiction by allowing the system to optimize between memory space and measurement precision based on actual operating conditions.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If deterministic counting mode is used to provide exact counts, then measurement precision is improved, but memory update rate requirements increase causing bottlenecks

Engineering Contradiction:
Improvecounting accuracyVSAvoidmemory update rate
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The system dynamically adjusts the counting mode based on traffic load. During high-load periods, statistical estimation is employed to reduce the memory update rate to manageable levels. During low-load periods, the system switches to deterministic counting to provide exact measurements. This dynamic switching resolves the contradiction by allowing the system to provide exact counts when possible while avoiding memory bottlenecks during high traffic.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If counter memory updates are performed at high rates to handle increasing event counts, then measurement precision is maintained, but device complexity and power consumption increase

Engineering Contradiction:
Improvereal-time counting accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The system dynamically selects the counting approach based on traffic load. When event rates are high, statistical estimation is used to reduce the frequency of memory updates, thereby reducing power consumption. When event rates are low, deterministic counting is used to maintain exact measurement accuracy. This dynamic adaptation resolves the contradiction by optimizing power consumption while maintaining measurement precision when necessary.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10333802B2Time efficient counters and meters architecture
Publication Date: 2019.06.25 MARVELL ASIA PTE LTD
  • US10333802B2 patent drawing
  • US10333802B2 patent drawing
  • US10333802B2 patent drawing

AI summary

A meter module for use in a network device comprises conformance circuitry configured to: access a first memory device storing a conformance indicator that indicates whether a permitted rate of packet traffic has been exceeded, and classify packets received at the network device based at least in part on the conformance indicator. Sampling circuitry is configured to, responsively to the conformance circuitry classifying the packets: sample events associated with at least some of the received packets, and generate indicators of the sampled events. Update circuitry is configured to: access a second memory device, slower than the first memory, to update a number of tokens stored in the second memory device, and access the first memory device to update the conformance indicator when the updated number of tokens indicates that the permitted rate of packet traffic has been exceeded.