Dual-mode Cryptographic Processing via CPU-Hardware Segmentation
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Solution Overview
Problem
Existing cryptographic operation methods are inefficient due to high latency and resource wastage, as they rely solely on hardware acceleration modules or CPU processing, leading to suboptimal use of computational resources when tasks are run concurrently.
Innovation Solution
Implementing dual-mode hardware acceleration by dividing data into blocks and offloading some to cryptographic hardware accelerators while performing others using native CPU instructions, based on availability and resource utilization conditions, to optimize resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all cryptographic operations are offloaded to hardware acceleration modules, then cryptographic performance is improved, but CPU cycles are wasted due to polling when hardware modules are busy
Solution Approach 1:
The patent segments cryptographic operations into two types: those offloaded to hardware acceleration modules and those executed by the CPU. The data is divided into multiple blocks, with some blocks processed by hardware and others by CPU, allowing the system to leverage both paths without wasting CPU cycles polling for hardware availability.
Solution Approach 2:
Instead of completely offloading all cryptographic operations to hardware (which would cause CPU waste when hardware is busy), the patent applies partial offloading where only some operations are sent to hardware while others are handled by CPU. This partial action approach optimizes resource utilization by avoiding both hardware bottlenecking and CPU polling waste.
2Device complexity
If all cryptographic operations are performed by CPU, then resource sharing is simplified, but computational efficiency deteriorates for heavy concurrent tasks
Solution Approach 1:
The patent segments the workload between CPU and hardware accelerators, with the CPU handling certain cryptographic operations directly while offloading others to dedicated hardware modules. This segmentation allows the system to maintain simple resource management for CPU tasks while leveraging hardware acceleration for computationally intensive operations, thereby improving overall productivity.
Solution Approach 2:
The system implements a dual-mode approach where the CPU can both execute cryptographic operations natively and manage hardware accelerator resources. This multi-functionality allows the CPU to adaptively choose the best execution path based on workload characteristics, maintaining resource management simplicity while achieving high computational efficiency through hardware utilization.
3Productivity
If hardware acceleration modules are used for cryptographic operations, then cryptographic performance is improved, but latency increases due to memory transfers and communication overhead
Solution Approach 1:
The patent segments cryptographic operations into those suitable for hardware acceleration (bulk data processing) and those better suited for CPU execution (smaller or latency-sensitive operations). By segmenting the workload, the system can leverage hardware throughput for large operations while avoiding the latency penalty of memory transfers for smaller operations that can be handled efficiently by the CPU.
Solution Approach 2:
The system applies partial offloading to hardware accelerators only for operations where the throughput benefit outweighs the latency cost. For operations where latency is critical or data size is small, the CPU handles them directly, avoiding the memory transfer overhead. This selective partial action approach optimizes the trade-off between throughput and latency.
Data Source
AI summary
Systems and methods for dual mode hardware acceleration for cryptographic operations are provided. According to one embodiment, data upon which a cryptographic operation is to be performed is receive by a computer system that includes a host CPU and a cryptographic hardware accelerator. The data is divided into multiple blocks. Performance of the operation on a first block is offloaded to the hardware accelerator. For each remaining block: (i) the CPU requests state information of the hardware accelerator; (ii) when the state satisfies a condition, then performance of the operation is offloaded to the hardware accelerator; (iii) otherwise, the operation is performed by the CPU by invoking a native hardware supported cryptographic instruction. In this manner, the cryptographic operation is performed on at least one of the blocks by the hardware accelerator and the operation is performed on at least another of the blocks by the CPU.