Dual-Mode Delay Chain Circuit for Fine Resolution With Fewer Stages
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Solution Overview
Problem
Current Vernier delay line implementations in digital phase locked loops face challenges in achieving both high accuracy and short delay path, requiring significant silicon area and high power consumption, with difficulties in implementing long delay lines due to precision and matching requirements.
Innovation Solution
A delay chain circuit with at least two delay elements, each operable in two modes, allowing for switching between a first and second delay period, using a mode selection switch and inverter circuit to optimize delay resolution and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a Vernier delay line is designed to provide high accuracy with fine delay resolution (e.g., 1 ps), then a large number of delay elements (e.g., 500 cells) are required to cover the desired delay range, but this results in significant silicon area consumption and high power consumption
Solution Approach 1:
The delay line is divided into multiple delay stages, where each stage can be independently controlled. This segmentation allows the system to achieve fine delay resolution by combining the output of multiple coarser stages, thereby reducing the total number of delay elements required while maintaining high accuracy.
Solution Approach 2:
The delay line employs dynamic control mechanisms where the delay amount of each stage can be adjusted based on the required total delay. This dynamic adaptability allows the system to achieve high resolution delay measurement without requiring a fixed large number of stages, thereby reducing silicon area consumption.
2Measurement precision
If a Vernier delay line is designed to provide high accuracy with fine delay resolution, then a large number of delay elements are required, but this also results in high power consumption due to the significant current required to drive the delay and comparison circuits
Solution Approach 1:
By segmenting the delay line into multiple independently controllable stages, the system can activate only the necessary number of stages for a given delay measurement, thereby reducing the total current consumption compared to activating all 500 delay elements continuously.
Solution Approach 2:
The system uses partial action by activating only a subset of delay stages required to achieve the desired delay range and resolution, rather than using all available stages. This partial utilization significantly reduces power consumption while maintaining the required measurement precision.
3Measurement precision
If a long delay line is implemented to achieve high accuracy, then precision and matching requirements become increasingly difficult to meet, but the dual-mode delay chain circuit allows switching between different delay periods to optimize performance
Solution Approach 1:
The delay chain circuit allows dynamic switching between different delay modes (e.g., fast mode and slow mode) depending on the required measurement range. This dynamic operation enables the system to achieve high accuracy without requiring an excessively long delay line, thereby simplifying manufacturing and reducing matching requirements.
Solution Approach 2:
The system changes the delay parameter by switching between different operational modes of the delay elements. By adjusting the delay period of each stage based on the required measurement range, the system can achieve high accuracy while avoiding the need for a fixed long delay line that would be difficult to manufacture with tight matching requirements.
Data Source
AI summary
A delay chain circuit including at least two delay elements, wherein each delay element is configured to: receive a first signal; output a second signal after a delay period; and be operable in at least two modes of operation wherein in a first mode of operation each delay element has a first delay period and in a second mode of operation each delay element has a second delay period.