Dual-Mode Frequency Divider With Retiming for Multi-Phase Clocks
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Solution Overview
Problem
Conventional frequency divider circuits face challenges in maintaining optimal phase relationships and processing speed due to restricted setup times, especially when handling high-speed signals and multi-phase clocks, which are crucial for applications like high-density computing and data transmission.
Innovation Solution
A dual-mode frequency divider circuit comprising a frequency dividing circuit and a retiming circuit, where the mode control signal determines the ratio of input and output clock periods, allowing for longer setup times and improved signal processing speed by using multiple retiming circuit units to generate intermediate and output clocks with optimized phase relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional frequency divider circuits use D-Flip Flops with fixed setup time requirements, then the circuit structure is simple, but the signal processing speed is restricted and cannot meet high-speed signal demands
Solution Approach 1:
The patent implements dynamic operation mode selection where the frequency divider can switch between first operation mode (higher speed) and second operation mode (lower speed) based on setup time requirements. The circuit dynamically adjusts its behavior by selecting different paths through the retiming circuits and mode control signals, allowing it to adapt to different speed requirements rather than being fixed to a single operating mode
Solution Approach 2:
The patent segments the frequency divider circuit into multiple retiming circuit units (first retiming circuit unit, second retiming circuit unit, etc.) that can be selectively activated. Each retiming unit processes clock signals independently and can be enabled or disabled based on the desired division ratio and setup time constraints, allowing the circuit to be divided into functional segments that operate independently
2Measurement precision
If the frequency divider circuit processes multi-phase clocks to maintain ideal phase relationships, then the phase accuracy is improved, but the setup time requirement becomes more difficult to meet due to increased signal path complexity
Solution Approach 1:
The patent uses retiming circuits to preliminarily adjust and stabilize the phase relationships of multi-phase clock signals before they reach the main frequency division logic. The retiming units pre-process the clock signals to establish correct phase alignments in advance, ensuring that when signals proceed through the division logic, the setup time requirements are already satisfied
Solution Approach 2:
The patent introduces intermediate retiming circuit units that act as mediators between the input multi-phase clocks and the main frequency division logic. These intermediary circuits buffer and condition the clock signals, isolating the main division logic from the complexity of multi-phase timing requirements and allowing each component to operate with relaxed timing constraints
3Reliability
If the circuit uses multiple retiming circuit units to generate intermediate clocks with optimized phase relationships, then the setup time compliance is improved, but the device complexity increases
Solution Approach 1:
The patent designs retiming circuit units with universal functionality that can serve multiple purposes: they can operate as simple buffer stages, as phase alignment circuits, or as frequency division stages depending on the mode control signal. Each retiming unit is multi-functional and can be configured differently based on operational requirements, reducing the need for separate dedicated circuits for each function
Data Source
AI summary
A frequency divider circuit is provided. The frequency divider circuit processes multiple input clocks. The frequency divider circuit includes a frequency dividing circuit and a retiming circuit. The frequency dividing circuit generates an intermediate clock according to a first subgroup of the input clocks. The retiming circuit generates multiple output clocks according to a second subgroup of the input clocks and the intermediate clock. The periods of the input clocks are all a first period, and the periods of the output clocks are all a second period. The first period is smaller than the second period. The frequency dividing circuit and the retiming circuit operate according to a mode control signal which determines a ratio of the first period to the second period.