Dual-Mode Delay Locked Loop for DDR Clock-DQS Alignment
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Solution Overview
Problem
In DDR DRAM operations, voltage fluctuations cause phase mismatch between the clock signal and the DQS signal, leading to data reading errors and reduced operational reliability due to misalignment of rising edges.
Innovation Solution
A delay locked loop circuit with a variable delay line and a control circuit that adjusts the delay in two modes using different step values, allowing for adaptive timing adjustments to align the clock signal with the DQS signal, improving synchronization and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage fluctuations occur during DDR DRAM operations, then the phase alignment between clock signal and DQS signal deteriorates, but maintaining fixed delay cannot adapt to dynamic voltage changes
Solution Approach 1:
The patent implements a dual-mode delay adjustment mechanism that dynamically adapts to voltage fluctuations. The control circuit switches between first mode (normal operation) and second mode (anomaly response) based on detected phase differences, enabling the delay line to respond dynamically to changing voltage conditions rather than maintaining a fixed delay setting
Solution Approach 2:
The patent employs a feedback mechanism where the control circuit continuously monitors the phase difference between the clock signal and DQS signal. When the phase difference exceeds a threshold (indicating voltage-induced anomalies), the system adjusts the delay line setting and provides feedback to maintain proper alignment, creating a closed-loop control system that compensates for voltage fluctuations
2Device complexity
If single-mode delay adjustment is used, then the control circuit complexity is reduced, but the response speed to timing anomalies is insufficient
Solution Approach 1:
The patent segments the delay adjustment function into two distinct modes with different step values. The first mode uses a coarse adjustment step for normal operations, while the second mode uses a finer adjustment step for anomaly correction. This segmentation allows the control circuit to optimize between speed and precision by selecting the appropriate mode based on the detected phase difference
3Productivity
If delay adjustment step value is increased, then the convergence speed of phase alignment is improved, but the precision of delay adjustment is reduced
Solution Approach 1:
The patent makes the delay adjustment step value dynamic by implementing two different step values selectable based on operational conditions. During normal operation (first mode), a larger step value accelerates convergence. When phase anomalies are detected (second mode), a smaller step value provides finer control for precise alignment, optimizing both speed and precision adaptively
Data Source
AI summary
A delay locked loop circuit includes: a variable delay line configured to delay an initial clock signal to generate a delayed clock signal; and a control circuit connected to the variable delay line, configured to control the variable delay line to perform delay adjustment of a first mode and further configured to perform delay adjustment of a second mode on the variable delay line when the delayed clock signal satisfies a preset condition. A step value of each delay adjustment of the first mode is a first step value, a step value of each delay adjustment of the second mode is a second step value, and the second step value is greater than the first step value.