Dual-Mode Frequency Synthesizer for Agile Tuning and Low Phase Noise

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Solution Overview

Problem

Radar systems face a tradeoff between frequency agility and phase-noise performance due to the degradation of phase-noise in direct digital synthesizers (DDS) when tuning resolution is high, while mix-and-multiply synthesizers offer better phase-noise but are large and expensive.

Innovation Solution

A dual-mode hybrid frequency synthesizer that combines the flexibility of DDS-based synthesizers with the low-noise performance of mix-and-multiply synthesizers by incorporating RF switches and additional circuitry to enable high-resolution tuning and low-phase-noise modes, allowing for injection of low-noise frequencies to bypass DDS-induced phase-noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a DDS-based synthesizer is used to achieve high resolution tuning, then frequency agility is improved, but phase-noise performance deteriorates

Engineering Contradiction:
Improvefrequency agilityVSAvoidphase-noise performance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system dynamically switches between DDS-based mode for high frequency agility and injection-based mode for low phase-noise performance. The RF switch enables real-time reconfiguration of the signal path, allowing the system to adapt its operating characteristics based on the specific application requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The synthesizer is divided into two functional paths: a DDS-based path for high-resolution frequency tuning and an injection-based path for low-phase-noise performance. These segments are combined through an RF switch that selects the appropriate path based on operational needs.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a mix-and-multiply synthesizer is used to achieve low phase-noise performance, then phase-noise performance is improved, but device size and cost increase

Engineering Contradiction:
Improvephase-noise performanceVSAvoiddevice size and cost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts only the essential low-phase-noise injection capability from the complex mix-and-multiply architecture, implementing it through a simplified RF switch-based system. This eliminates the need for multiple RF modules while retaining the low phase-noise benefit.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system uses a cost-effective DDS device combined with simple RF switching circuitry instead of expensive mix-and-multiply synthesizer hardware. The RF switch acts as a simple, low-cost component that enables the system to achieve low phase-noise performance without requiring complex and expensive dedicated RF modules.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If multiple RF modules are used in a mix-and-multiply synthesizer to generate discrete offset frequencies, then phase-noise performance is improved, but device complexity increases

Engineering Contradiction:
Improvephase-noise performanceVSAvoidnumber of RF modules
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The RF switch serves multiple functions: it selects between DDS output and injection signals, enables or disables the DDS based on operating mode, and routes signals to the appropriate output path. This multi-functional component replaces what would otherwise require multiple dedicated RF modules.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP2853026B1Hybrid dual mode frequency synthesizer circuit
Publication Date: 2018.07.25 RAYTHEON CO
  • EP2853026B1 patent drawingFigure 1
  • EP2853026B1 patent drawingFigure 2
  • EP2853026B1 patent drawingFigure 3

AI summary

A dual mode frequency synthesizer circuit including: a DDS or PLL (204) for receiving an input clock (202) and generating an output clock (206), in a high resolution mode; and an RF switch (210) having its output (208) coupled to the output of the DDS or PLL, a first input (216) for receiving a first injection low phase-noise clock (F1), a second input (218) for receiving a second injection low phase-noise clock (F2), and a control input (222) for selecting one of the first or second injection low phase-noise clocks for a low phase- noise mode.