Dual-Mode Frequency Multiplier With Switchable Harmonic Rejection
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Solution Overview
Problem
Existing frequency multiplier designs for gigahertz-band transceivers suffer from low output power, insufficient harmonic rejection, and increased system complexity, particularly when operating in multiple mm-wave bands like 28 and 39 GHz, due to complex frequency generation circuitry and phase noise issues.
Innovation Solution
A dual-mode frequency multiplier incorporating a switchable phase shifter and nonlinear elements driven by differential signals to produce in-phase even and out-of-phase odd harmonics, allowing for configurable harmonic rejection by switching between 0° and 180° phase shifts, enabling frequency doubling or tripling within a single transceiver architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex frequency generation circuitry including paralleled multiplier and amplifier chains is used, then frequency multiplication capability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple multiplier chains into a single integrated frequency multiplier circuit that can operate in different modes (doubler, tripler, quadrupler) by switching the input signal frequency and phase, eliminating the need for separate paralleled multiplier and amplifier chains for each frequency band
Solution Approach 2:
The frequency multiplier is designed as a universal circuit that can perform multiple functions (frequency doubling, tripling, quadrupling) depending on the input frequency and phase configuration, replacing the need for dedicated circuits for each frequency band (28 GHz, 39 GHz, etc.)
2Device complexity
If self-mixing or injection locking is used in frequency multipliers, then circuit simplicity is improved, but output power decreases
Solution Approach 1:
The patent employs dynamic switching between different operating modes (doubler, tripler, quadrupler) and uses active phase shifting to optimize output power for each mode, rather than relying on static self-mixing or injection locking mechanisms
3Adaptability or versatility
If multiple VCOs or multi-mode VCO are used, then frequency reconfigurability is improved, but phase noise performance deteriorates
Solution Approach 1:
The patent uses a single VCO whose output is fed into a reconfigurable frequency multiplier that can dynamically switch between different multiplication modes (2x, 3x, 4x), eliminating the need for multiple VCOs while maintaining phase noise performance
4Ease of manufacture
If existing multi-band components are used in transceivers, then cost reduction is improved, but performance adequacy worsens
Solution Approach 1:
The patent designs a universal frequency multiplier and transceiver architecture that can operate across multiple frequency bands (28 GHz, 39 GHz, and others) using the same components, achieving both cost reduction through component reuse and adequate performance through optimized frequency multiplication and phase shifting
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high harmonic rejection and sufficient output power across both frequency bands with minimal phase noise and system complexity, enabling efficient operation in dual-band transceivers for 5G communication systems.
Implementation Method 1
The first and second nonlinear elements are driven by a differential signal to produce a first and a second branch signal each having even and odd harmonics
Implementation Method 2
The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180°
Implementation Method 3
Switching the switchable phase shifter between 0° and 180° suppresses either the odd or the even harmonics from the combined signal
Data Source
AI summary
One illustrative dual mode frequency multiplier embodiment includes: a first and a second nonlinear element, a summation node, and a switchable phase shifter. The first and second nonlinear elements are driven by a differential signal to produce a first and a second branch signal each having even and odd harmonics, the even harmonics being in-phase and the odd harmonics being out of phase. The first and second branch signals combine at the summation node to form a combined signal. The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180° to suppress either the odd or the even harmonics from the combined signal.