Dual-Mode Image Processor Circuit for Two-Pixel and Picture-in-Picture

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Solution Overview

Problem

Existing display systems requiring two sets of image processor circuits for two-pixel mode increase circuit area and result in idle processors when not in use, inefficiently utilizing resources.

Innovation Solution

An image processor circuit with dual processor circuits that can operate in both two-pixel and picture-in-picture modes, processing different parts of input data simultaneously using shared resources to minimize circuit area and avoid idle processors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If two sets of image processor circuits are disposed to support two-pixel mode, then the processing capability for high pixel rate images is improved, but the circuit area increases and one processor will be idle when two-pixel mode is not needed

Engineering Contradiction:
Improveprocessing capability for high pixel rate imagesVSAvoidcircuit area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent makes a single image processor circuit capable of performing multiple functions by supporting both two-pixel mode and picture-in-picture mode. The same processor circuit can process different input data streams for different display modes, eliminating the need for dedicated hardware for each mode and reducing overall circuit area while maintaining high processing capability when needed

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If two sets of image processor circuits are disposed to support two-pixel mode, then the processing capability for high pixel rate images is improved, but one processor will be idle when two-pixel mode is not needed

Engineering Contradiction:
Improveprocessing capability for high pixel rate imagesVSAvoidprocessor utilization flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic mode switching capability where the image processor circuit can adaptively change its operating mode based on real-time display requirements. The circuit transitions between two-pixel mode and picture-in-picture mode dynamically, ensuring that the processor remains actively utilized across different operational scenarios and avoiding idle states

Inventive Principle:
Principle #15Dynamics

3Area of stationary object

If a single image processor circuit is used, then the circuit area is reduced, but the processing capability for high pixel rate images in two-pixel mode is insufficient

Engineering Contradiction:
Improvecircuit areaVSAvoidprocessing capability for high pixel rate images
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

The patent achieves enhanced processing capability within a single circuit by changing operational parameters such as clock frequency and data processing throughput. The image processor circuit operates at higher clock frequencies and processes data at increased rates to compensate for having only one processor, thereby maintaining high pixel rate image processing capability without requiring additional hardware

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12405763B2Image processor circuit supporting two-pixel mode and picture-in-picture mode and image processing method thereof
Publication Date: 2025.09.02 REALTEK SEMICON CORP
  • US12405763B2 patent drawing
  • US12405763B2 patent drawing
  • US12405763B2 patent drawing

AI summary

An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. In a picture-in-picture mode, the first processor circuit is configured to process second input data to generate main-picture output data and the second processor circuit is configured to process third input data to generate sub-picture output data for the display panel to display.