Dual mode interconnect
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Solution Overview
Problem
Existing data processing systems face challenges in efficiently transferring data between data processing engines in a System on a Chip (SoC) due to limitations in deterministic and non-deterministic data routing, particularly in achieving low latency and high bandwidth communication across neighboring and non-neighboring engines.
Innovation Solution
The implementation of a dual-mode interconnect that supports both circuit switching and packet switching, allowing for reserved point-to-point communication paths in circuit switching mode and shared physical wires in packet switching mode, with configurable ports and arbitration mechanisms to manage data routing efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If circuit switching mode is used for data transfer, then deterministic low latency is achieved, but routing flexibility and adaptability are reduced
Solution Approach 1:
The interconnect system dynamically switches between circuit switching mode (for deterministic low-latency communication) and packet switching mode (for flexible adaptive routing) based on communication requirements. This dynamic mode selection allows the system to optimize for either low latency or routing flexibility depending on the specific data transfer needs between processing engines.
2Adaptability or versatility
If packet switching mode is used for data transfer, then routing flexibility and bandwidth utilization are improved, but deterministic timing and latency predictability are lost
Solution Approach 1:
The system employs dynamic mode selection where packet switching is activated for applications requiring high routing flexibility and bandwidth utilization, while circuit switching is activated when deterministic timing is critical. This allows each data transfer operation to use the most appropriate switching mode for its specific requirements.
3Loss of time
If dedicated point-to-point paths are reserved for each communication, then deterministic low latency is achieved, but interconnect complexity and resource utilization increase
Solution Approach 1:
The interconnect uses dynamic path allocation where dedicated point-to-point paths are established on-demand for circuit switching operations rather than being permanently reserved. This allows the system to achieve deterministic low latency when needed while maintaining lower overall complexity by sharing physical infrastructure across multiple logical connections.
4Productivity
If shared physical wires are used for multiple logical streams, then bandwidth utilization and resource efficiency are improved, but data routing complexity and arbitration requirements increase
Solution Approach 1:
The shared physical interconnect is segmented into multiple virtual channels or logical streams, each capable of independent data flow. This segmentation allows multiple logical streams to share the same physical wires efficiently while maintaining separate routing control for each stream, thus improving bandwidth utilization without excessive routing complexity.
Solution Approach 2:
An arbitration mechanism acts as an intermediary between multiple logical streams sharing the same physical wires. The arbiter manages access to shared resources, allocating bandwidth fairly among different streams and handling routing decisions, thereby enabling efficient shared wire usage while controlling routing complexity through centralized management.
Data Source
AI summary
Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.