Dual-Mode Interconnect for Data Processing Engine Array Communication
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Solution Overview
Problem
Existing data processing engine arrays face challenges in efficiently transferring data between processing engines due to limitations in deterministic and non-deterministic data routing, particularly in achieving low latency and high bandwidth communication across the array.
Innovation Solution
The implementation of a System on a Chip (SoC) with an interconnect that supports both circuit switching and packet switching modes, allowing for deterministic data routing through reserved point-to-point communication paths and non-deterministic routing using shared physical wires, respectively, enables efficient data transfer between data processing engines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If circuit switching mode is used for data routing, then deterministic latency is achieved, but routing flexibility and adaptability are reduced
Solution Approach 1:
The interconnect switch is designed to dynamically reconfigure its switching mode between circuit switching and packet switching based on real-time traffic requirements. This dynamic adaptability allows the system to provide deterministic low-latency communication when needed (circuit switching) while maintaining routing flexibility for other scenarios (packet switching), thus resolving the contradiction between deterministic latency and routing flexibility.
2Adaptability or versatility
If packet switching mode is used for data routing, then routing flexibility is improved, but deterministic latency cannot be guaranteed
Solution Approach 1:
The interconnect switch segments its ports into different groups that can operate in different switching modes simultaneously. Some ports are dedicated to circuit switching for deterministic latency requirements, while other ports operate in packet switching mode for routing flexibility. This segmentation allows the system to provide both deterministic latency and routing flexibility without compromise.
3Reliability
If dedicated point-to-point communication paths are reserved, then deterministic data transfer is achieved, but interconnect complexity increases
Solution Approach 1:
The interconnect switch implements dynamic path establishment and teardown mechanisms that allow dedicated point-to-point communication paths to be reserved only when deterministic data transfer is required. When such requirements are not present, the interconnect reconfigures to share physical wires among multiple communication flows, thereby reducing interconnect complexity while maintaining deterministic transfer capability when needed.
Data Source
AI summary
Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.