Dual-Mode I/O Buffer for Parallel Analog and Digital SoC Testing
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Solution Overview
Problem
The high complexity and cost of manufacturing test coverage for Systems on a Chip (SoC) are exacerbated by the need for numerous analog test pins, which limit digital test pin availability and increase test time due to the limited channels provided by Automated Test Equipment.
Innovation Solution
Implementing dual function input/output buffers that can operate as both analog and digital connections, allowing for dynamic allocation of test connections to optimize parallel testing without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated analog test pins are used to enable parallel testing of analog modules, then analog test coverage is improved, but the number of available digital test pins decreases and package cost increases
Solution Approach 1:
The patent implements I/O buffers that can dynamically switch between analog and digital modes, allowing the same physical pin to serve multiple functions. The buffer circuitry includes switchable paths that connect the I/O pin to either analog modules or digital modules based on test requirements, eliminating the need for dedicated analog test pins and maximizing pin utilization.
2Productivity
If dedicated analog test pins are used to enable parallel testing of analog modules, then analog test coverage is improved, but test time for digital logic increases
Solution Approach 1:
The patent employs dynamic mode switching capability where the I/O buffer can be reconfigured between analog and digital modes during test operations. This dynamic allocation allows the test system to optimize pin usage in real-time, enabling parallel testing of both analog and digital modules using the same physical infrastructure, thereby reducing overall test time.
3Strength
If I/O buffer operates in digital mode with low impedance output, then digital signal drive capability is improved, but analog module isolation is compromised
Solution Approach 1:
The patent implements different impedance characteristics for different operational modes within the same I/O buffer circuit. When operating in digital mode, the output presents a low impedance state for strong digital signal drive capability. When operating in analog mode, the output transitions to a high impedance state to provide isolation from digital circuits, ensuring clean analog signal paths without digital interference.
Solution Approach 2:
The I/O buffer dynamically switches between low impedance (digital mode) and high impedance (analog mode) states based on the selected operational mode. This dynamic impedance control is achieved through switchable circuit paths that reconfigure the buffer's output characteristics, allowing the same hardware to optimize for either digital signal strength or analog isolation as needed.
Data Source
AI summary
A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.