Matrix Multiplication Accelerators With Dual-Mode Vector Circuits
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Solution Overview
Problem
Existing processors face inefficiencies in performing vector and matrix multiplication operations, particularly in handling different numerical formats such as fixed-point, floating-point, and Flexpoint, leading to increased circuit area and power consumption.
Innovation Solution
A hardware accelerator that includes a single circuit capable of performing both fixed-point and floating-point operations by using a mode controller to switch between modes, minimizing exponent comparison, shifting, leading zero detection, and normalization processes, and utilizing a shared exponent for Flexpoint operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate circuits are used for fixed-point and floating-point operations, then operational precision is maintained, but circuit area and power consumption increase
Solution Approach 1:
The patent combines fixed-point and floating-point operational circuits into a single shared circuit. The circuit can be configured to perform either fixed-point or floating-point operations based on control signals, eliminating the need for separate dedicated circuits for each numerical format while maintaining the precision requirements of both operation types.
Solution Approach 2:
The operational circuit is designed with multi-functionality to handle both fixed-point and floating-point operations. By incorporating configuration control mechanisms and adaptive processing logic, the same circuit infrastructure serves multiple numerical format requirements, reducing overall circuit area while preserving operational precision for each format.
2Reliability
If separate circuits are used for fixed-point and floating-point operations, then operational reliability is maintained, but power consumption increases
Solution Approach 1:
The patent merges fixed-point and floating-point operational circuits into one shared circuit resource. This consolidation reduces the total number of active circuit components, thereby lowering power consumption while maintaining operational reliability through controlled switching between operation modes and appropriate precision management for each numerical format.
Solution Approach 2:
The circuit incorporates dynamic configuration capabilities that allow it to adapt its operational characteristics based on the required numerical format. By dynamically adjusting its state and configuration rather than maintaining separate static circuits, the system reduces power consumption while ensuring reliable operation for both fixed-point and floating-point computations.
3Productivity
If multiple dedicated circuits are implemented for different numerical formats, then processing speed is maintained, but device complexity increases
Solution Approach 1:
The patent implements a universal operational circuit that can process both fixed-point and floating-point operations. This multi-functional approach reduces device complexity by eliminating redundant circuitry while maintaining processing speed through efficient mode switching and optimized computational pathways within the shared circuit architecture.
Solution Approach 2:
The circuit employs dynamic configuration and control mechanisms that allow it to optimize its operational characteristics for different numerical formats in real-time. This dynamic adaptability reduces device complexity compared to static dedicated circuits, while maintaining high processing speeds through efficient resource utilization and minimized reconfiguration overhead.
4Area of stationary object
If a single circuit handles multiple numerical formats, then circuit area and power consumption are reduced, but operational precision may be compromised
Solution Approach 1:
The patent applies local quality by implementing precision-specific processing stages within the shared circuit. Different portions of the circuit are optimized for specific numerical formats, with appropriate precision handling logic activated based on the operational mode. This ensures that each numerical format receives the precision treatment it requires while sharing the overall circuit infrastructure.
Solution Approach 2:
The circuit utilizes parameter changes to adapt its operational characteristics based on the required numerical format. By dynamically adjusting precision parameters, data representation formats, and computational accuracy settings, the single circuit maintains operational precision for both fixed-point and floating-point operations while benefiting from reduced circuit area through resource sharing.
Data Source
AI summary
Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described. A combined fixed-point and floating-point vector multiplication circuit may include at least one switch to change the circuit between a first mode and a second mode. In the first mode, the circuit is to multiply mantissas from a same element position of a first floating-point vector and a second floating-point vector to produce a product, shift the products, produce signed representations of the shifted products, add the signed representations of the shifted products to produce a single product, and normalize the single product into a single floating-point resultant. In the second mode, the circuit is to multiply values from a same element position of a first integer vector and a second integer vector to produce a corresponding product, and add each corresponding product to produce a single integer resultant.