Dual-Mode Memory Cell With Antifuse and Latch
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Solution Overview
Problem
Current memory technologies lack a solution for a memory cell that can seamlessly transition between non-volatile and volatile memory modes, with non-volatile memories having slower access speeds and higher operating voltages, and volatile memories losing data upon power interruption.
Innovation Solution
A memory cell design incorporating a latch, antifuse elements, and select transistors, allowing for selective operation as either non-volatile or volatile, with antifuse elements programmed to store complementary data and a latch enabled or disabled based on voltage levels, enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory is used, then data retention is improved, but access speed deteriorates
Solution Approach 1:
The memory cell is segmented into two distinct portions: a non-volatile memory portion (antifuse elements) for data retention and a volatile memory portion (latch circuit) for fast access. This segmentation allows each portion to optimize its function while working together as an integrated memory cell.
Solution Approach 2:
The patent merges non-volatile antifuse elements with a volatile latch circuit into a single memory cell structure. The antifuse elements provide non-volatile data storage while the latch circuit enables volatile memory operations, combining the advantages of both memory types.
2Reliability
If non-volatile memory is used, then data retention is improved, but operating voltage requirement increases
Solution Approach 1:
The memory cell dynamically switches between different operational modes (non-volatile and volatile) based on the state of the select transistors. When select transistors are off, the cell operates in non-volatile mode requiring higher voltage for programming. When select transistors are on, it operates in volatile mode with lower voltage for read/write operations.
Solution Approach 2:
The operating voltage parameter is changed based on the operational mode. Higher voltages are applied only when needed for programming the antifuse elements, while normal operations use lower voltages through the latch circuit, effectively managing power consumption.
3Speed
If volatile memory is used, then access speed is improved, but data retention deteriorates
Solution Approach 1:
The latch circuit is pre-configured with cross-coupled inverters that are capable of rapidly latching data. This preliminary structure enables fast access operations while the antifuse elements are pre-programmed to provide the non-volatile data source, ensuring both speed and retention capabilities are ready when needed.
4Adaptability or versatility
If dual-mode memory cell is implemented, then versatility is improved, but device complexity increases
Solution Approach 1:
The memory cell is designed with universal functionality to operate in both non-volatile and volatile modes using the same basic structure. The latch circuit and antifuse elements work together to provide multiple memory operation modes, eliminating the need for separate memory cells for different functions.
Solution Approach 2:
By segmenting the cell into modular components (latch portion and non-volatile portion with select transistors), the complexity is managed through clear functional separation. Each segment has a defined role, making the overall complex structure more controllable and manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The memory cell can function as both non-volatile and volatile, offering flexible data storage and retrieval with improved access speed and power management, addressing the limitations of existing memory technologies.
Implementation Method 1
a first oxide capacitor and a second oxide capacitor are coupled to the first and second connections respectively. Both the first and second oxide capacitors are coupled to receive a programming signal at a third voltage that may be operable to rupture either one of the first or second oxide capacitor.
Implementation Method 2
The memory circuit, depending on the configuration of the programmable switches and the back-to-back inverters, may operate as a ROM that stores a logic high value, a ROM that stores a logic low value, or a RAM.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
A memory cell includes a latch, two antifuse elements, and two select transistors. The latch is connected with a first node and a second node, and receives a first power voltage and a second power voltage. The latch is selectively enabled or disabled according to an enable line voltage. The first antifuse element is connected with the first node and an antifuse control line. The second antifuse element is connected with the second node and the antifuse control line. The gate terminal, the first drain/source terminal and the second drain/source terminal of the first select transistor are connected with a word line, the first node and a bit line, respectively. The gate terminal, the first drain/source terminal and the second drain/source terminal of the second select transistor are connected with the word line, the second node and an inverted bit line, respectively.