Dual-Mode Memory Chip for Hierarchical Interleaved Configurations
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Solution Overview
Problem
Standardized memory modules optimized for low-end systems are inefficient when used in larger systems, leading to potential losses in efficiency and increased costs due to the need for custom designs to meet different system requirements.
Innovation Solution
A dual-mode memory chip that supports both daisy-chained and hierarchical interleaved configurations, allowing for a larger volume of memory to be configured with a limited number of buses and achieving power savings by reducing bus operations and I/O ports, while maintaining compatibility with standardized modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standardized memory modules optimized for low-end systems are used in larger systems, then compatibility and ease of manufacture are improved, but system efficiency and performance deteriorate
Solution Approach 1:
The memory chip incorporates a mode register that can be configured at initialization to switch between daisy-chain mode and hierarchical interleaved mode. This dynamic reconfiguration allows the same standardized chip to adapt to different system requirements, maintaining both ease of manufacture through standardization and system efficiency through appropriate mode selection for larger systems.
Solution Approach 2:
The invention changes the operational parameters of the memory chip by enabling two distinct modes of operation. In daisy-chain mode, chips are accessed sequentially, while in hierarchical interleaved mode, multiple chips are accessed simultaneously with interleaved addressing. This parameter change allows standardized chips to achieve high performance in large-system configurations without requiring custom design.
2Productivity
If custom memory module designs are used to meet different system requirements, then system efficiency is improved, but device complexity and manufacturing costs increase
Solution Approach 1:
The memory chip is designed with universal functionality to operate effectively in both low-end and large-system configurations. By incorporating the mode register and supporting both daisy-chain and hierarchical interleaved modes, a single standardized chip design replaces the need for separate custom designs, reducing device complexity while maintaining system efficiency through appropriate mode selection.
3Quantity of substance
If more memory chips are added to increase memory capacity, then memory capacity is improved, but power consumption and bus operation complexity increase
Solution Approach 1:
The invention segments the memory system into multiple chips organized in a hierarchical interleaved structure. Instead of using a single large memory module or a simple daisy chain, the system divides memory capacity across multiple standardized chips that can be accessed independently and simultaneously. This segmentation increases memory capacity while reducing power consumption by distributing the access load across multiple chips rather than requiring one large chip or sequential access through a long daisy chain.
Solution Approach 2:
The hierarchical interleaved mode enables continuous useful action by allowing multiple memory chips to be accessed simultaneously with interleaved addressing. Instead of sequentially accessing chips in a daisy chain (which creates idle time and increases power consumption), the system maintains continuous productive memory operations across multiple chips, improving both capacity utilization and power efficiency.
Data Source
AI summary
A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.