Dual-Mode Memory Controller with Registering Clock Driver
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Solution Overview
Problem
Current memory systems face bandwidth limitations in intensive computing applications, making it difficult for the interface between the CPU and memory module to meet the high data throughput requirements.
Innovation Solution
A memory controller with a registering clock driver and data buffers that operate in two modes, allowing for enhanced data access and exchange between memory blocks and the host controller, utilizing multiple data buses to increase bandwidth and support intensive computing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional memory buffer chip with single data bus is used, then the structure is simple, but the bandwidth between CPU and memory module is insufficient for intensive computing applications
Solution Approach 1:
The patent divides the memory buffer chip into multiple independent data buffers (first data buffer and second data buffer), each capable of handling data transactions separately. This segmentation allows parallel data access through multiple data buses, thereby increasing bandwidth while maintaining manageable complexity through modular design
Solution Approach 2:
The patent transitions from a single-data-bus architecture to a multi-data-bus architecture by adding spatial dimension to data transmission. Multiple data buses operate in parallel, creating additional transmission pathways that increase bandwidth without proportionally increasing structural complexity
2Adaptability or versatility
If the memory controller operates in dual-mode (first mode and second mode), then the adaptability to different computing scenarios is improved, but the control complexity increases
Solution Approach 1:
The patent implements a dynamic switching mechanism between first mode and second mode through mode switching signals. The memory controller can adapt its operation dynamically based on computing scenarios: first mode for general memory access and second mode for intensive computing operations, thereby achieving versatility without permanent complexity increase
Solution Approach 2:
The memory controller is designed with multi-functionality to handle both conventional memory access operations and intensive computing operations through two distinct modes. The same hardware infrastructure supports multiple operational scenarios, reducing the need for separate dedicated systems and managing complexity through unified design
3Productivity
If multiple data buses are used for data exchange between memory blocks and data buffer, then the data throughput is improved, but the signal routing complexity increases
Solution Approach 1:
The patent segments data transmission into multiple independent data buses, each handling specific data flows between memory blocks and data buffers. This segmentation increases data throughput by enabling parallel transmission while managing routing complexity through organized, dedicated pathways for each bus
Data Source
AI summary
The application discloses a memory controller coupled to a memory module for controlling access to the memory module, wherein the memory module comprises one or more memory groups each having a plurality of memory blocks, and the memory controller comprising: a registering clock driver coupled to the memory module for providing to the memory module a data access command so as to control access to the memory module; one or more data buffers coupled to the registering clock driver, and each data buffer coupled to a memory group via a memory group data interface; wherein at least one of the memory group data interfaces comprises a plurality of data buses each coupled to one or more memory blocks of the memory group that the memory group data interface coupled to, such that the memory group can exchange data with the data buffer via the plurality of data buses under the control of the registering clock driver.