Dual-Mode Memory Controller I/O Circuit for High-Speed Data Transfer
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Solution Overview
Problem
Computer system memory performance often lags behind processor speed, limiting system performance improvements, and existing solutions to enhance memory bandwidth and capacity are costly.
Innovation Solution
A dual-mode memory controller with an I/O circuit that can switch between parallel and serial interconnects, using differential signaling techniques to connect memory modules and buffer units, enabling higher data transfer rates while maintaining cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel interconnect is used to connect memory modules, then compatibility with memory specifications is maintained, but data transfer rate is limited
Solution Approach 1:
The I/O circuit is designed to dynamically switch between parallel and serial interconnect modes based on the connected memory module type. The mode selection signal transitions the circuit from parallel mode (for traditional memory modules) to serial mode (for buffer units), enabling adaptive optimization of data transfer rates while maintaining broad compatibility across different memory specifications
Solution Approach 2:
The dual-mode I/O circuit serves multiple functions: it operates as a parallel interconnect for traditional memory modules and as a serial interconnect for buffer units. This multi-functionality allows a single circuit design to support both legacy parallel memory interfaces and modern high-speed serial interfaces, resolving the contradiction between speed optimization and specification compatibility
2Productivity
If serial interconnect is used to connect buffer units, then data transfer rate increases, but circuit complexity increases
Solution Approach 1:
The patent merges the parallel and serial interconnect functions into a single dual-mode I/O circuit. By combining both interconnect capabilities in one circuit design, the system achieves high memory bandwidth through serial mode while avoiding the complexity of maintaining separate parallel and serial circuit paths. The mode selection mechanism integrates both functions seamlessly
3Speed
If traditional parallel memory interface is used, then cost is reduced, but memory performance lags behind processor speed
Solution Approach 1:
The system changes the interconnect parameter from parallel to serial mode when operating with buffer units. This parameter change enables significantly higher data transfer rates that match modern processor speeds, while the underlying cost-effective memory module architecture remains unchanged. The serial mode activation only when needed allows performance optimization without permanently increasing system cost
Data Source
AI summary
A memory controller including a dual-mode memory interconnect includes an input/output (I/O) circuit including a plurality of input buffers and a plurality of output drivers. The I/O circuit may be configured to operate in one of a first mode and a second mode dependent upon a state of a mode selection signal. During operation in the first mode, the I/O circuit may be configured to provide a parallel interconnect for connection to one or more memory modules. During operation in the second mode, the I/O circuit may be configured to provide a respective serial interconnect for connection to each of one or more buffer units, each configured to buffer memory data that is being read from or written to the one or more memory modules.