Dual-Mode Memory Structure for LSSD and Muxed Flop Testing
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Solution Overview
Problem
Conventional memory circuit designs do not allow for simultaneous testing of logic that includes both Level Sensitive Scan Design (LSSD) and multiplexed flip-flop (muxed flop) scan elements, limiting the testability of integrated circuit devices in both ASIC and foundry environments.
Innovation Solution
A memory structure with multiplexers that selectively couple data and address paths between external and internal connections, enabling a dual scan architecture that supports both LSSD and muxed flop scan elements, and flush logic to direct data for observation during testing, facilitating complete testability across different environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate embedded memory designs are used for ASIC and foundry chip designs, then each design can be optimized for its specific test environment, but development time and costs increase
Solution Approach 1:
The memory circuit is designed with dual-mode capability that allows it to function in both LSSD scan mode and muxed-flop scan mode. This is achieved through mode control signals that configure the memory circuit to interface with different scan chain architectures, enabling a single design to serve both ASIC and foundry test environments without requiring separate designs
2Loss of time
If a single embedded memory design is used for both ASIC and foundry chip designs, then development time and costs are reduced, but complete testability of logic in both environments cannot be achieved
Solution Approach 1:
The memory circuit incorporates dynamic reconfiguration capability through mode control signals that can switch the circuit's operational mode. During ASIC testing, the circuit is configured for LSSD scan operation, while during foundry testing, it is reconfigured for muxed-flop scan operation. This dynamic adaptability ensures complete testability in both environments using a single design
3Device complexity
If conventional memory circuit designs are used, then simplicity is maintained, but simultaneous testing of both LSSD and muxed flop scan elements is not possible
Solution Approach 1:
The memory circuit uses mode control parameters (control signals) to change its operational characteristics. By adjusting these control parameters, the circuit can be configured to support either LSSD scan or muxed-flop scan testing protocols, enabling comprehensive test coverage for both scan element types without requiring fundamentally different circuit implementations
Data Source
AI summary
A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is further configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, thereby facilitating observation of the memory logic connection at the customer chip, wherein test elements of the memory structure comprise a scan architecture of a first type, and test elements of the customer chip comprise a scan architecture of a second type.