Dual-Mode Pass Gate Receiver for 1.8V and 3.3V Signals
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Solution Overview
Problem
Conventional low supply voltage integrated circuit technology struggles to effectively receive high and low voltage signals, particularly failing to support low voltage differential signaling standards due to limitations in NMOS devices and requiring additional PMOS devices for high voltage signals.
Innovation Solution
An integrated circuit design incorporating a single-ended driver with both NMOS and PMOS transistors, where a PMOS pass gate is coupled in parallel with an NMOS transistor to form different pass gates for low and high voltage modes, enabling the reception of input signals up to 3.3V while protecting against over and undershoots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an NMOS device is used to down level-shift the input signal in 1.8V integrated circuit technology, then the receiver is protected from high voltage damage, but the device cannot drive the input signal when the input signal is a high common-mode signal or LVCMOS18 signal
Solution Approach 1:
The pass gate is designed to perform multiple functions by combining NMOS and PMOS transistors in parallel, enabling it to handle both low voltage signals (LVDS, LVCMOS18) and high voltage signals (LVCMOS33, HSTL) through a single unified structure, thus achieving multi-functionality
2Adaptability or versatility
If a PMOS device is added to the pass gate in parallel with the NMOS device to support high voltage signals, then the device can transmit LVCMOS33 and HSTL signals, but the device complexity increases
Solution Approach 1:
The pass gate employs dynamic control through enable signals that selectively activate or deactivate the PMOS and NMOS transistors based on the input signal voltage level. This dynamic operation allows the circuit to adapt its configuration in real-time, supporting multiple voltage standards without requiring complex permanent circuitry for each standard
3Adaptability or versatility
If the PMOS pass gate is enabled for low voltage mode, then LVDS and LVCMOS18 signals can be transmitted, but high voltage signals cannot be properly handled
Solution Approach 1:
The circuit incorporates voltage detection mechanisms that monitor the input signal level and automatically switch between PMOS and NMOS transistor configurations. This feedback-based switching ensures that the appropriate transistor type is activated based on the input voltage level, maintaining reliability across different voltage standards
Data Source
AI summary
Methods and apparatus for receiving high voltage signals using a receiver designed in a low supply voltage technology are disclosed. One embodiment of an integrated circuit includes a single ended driver including an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor. An input pass gate is coupled to the single ended driver, and is configured as a PMOS pass gate coupled in parallel with the NMOS transistor in the single ended driver. In a low voltage mode, the NMOS transistor and the PMOS pass gate form a first pass gate for transmitting the input signal to the receiver. In a high voltage mode, the PMOS pass gate is disabled, and the NMOS transistor and PMOS transistor form a second pass gate for transmitting the input signal to the receiver.