Dual-Mode Patrol Read Controller for NAND Flash Memory

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Solution Overview

Problem

Current memory systems, such as SSDs with NAND flash memory, face challenges in efficiently performing patrol-read operations to detect data errors and manage block reliability, particularly in balancing data integrity with host-read command processing latency and power consumption.

Innovation Solution

The memory system employs a dual-mode patrol-read operation, switching between a first mode that optimizes power and time consumption when no host-read commands are pending and a second mode that minimizes latency impact during host-read command processing, using a controller to dynamically select the mode based on system status and operational needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a patrol-read operation is executed to detect data errors, then data integrity is improved, but power consumption and time consumption increase

Engineering Contradiction:
Improvedata integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic mode switching between first and second patrol-read modes based on real-time detection of host-read commands. The controller monitors the command queue and adjusts the patrol-read operation accordingly: when no host-read commands are pending, the system executes the first mode (comprehensive patrol-read); when host-read commands are detected, the system switches to the second mode (reduced patrol-read). This dynamic adaptation resolves the contradiction by making power consumption flexible rather than fixed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the patrol-read operation by implementing two distinct modes with different read scopes. The first mode reads all data in a physical block, while the second mode reads only specific pages or uses cached data. This parameter change allows the system to adjust the balance between data integrity checking and power consumption based on system state, resolving the technical contradiction.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a patrol-read operation is executed to detect data errors, then data integrity is improved, but processing time increases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller dynamically adjusts the patrol-read operation based on the presence of host-read commands. When host-read commands are detected, the system switches to the second mode that reduces processing time by reading only necessary data or using cached data, while still maintaining adequate data integrity checking. This dynamic adjustment resolves the time contradiction.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies partial action by implementing the second patrol-read mode that reads only specific portions of data (such as only certain pages or only data from specific channels) rather than performing a complete patrol-read of the entire physical block. This partial action reduces processing time while maintaining sufficient data integrity detection capability.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If a patrol-read operation is executed, then data integrity is improved, but latency impact on host-read commands increases

Engineering Contradiction:
Improvedata integrityVSAvoidhost-read command processing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system dynamically switches between patrol-read modes based on the detection of host-read commands. When host-read commands are present in the queue, the controller activates the second mode that minimizes interference with host-read operations. This dynamic response ensures that data integrity checking does not significantly impact host-read command processing speed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The controller acts as an intermediary that coordinates between the patrol-read operation and host-read commands. By detecting host-read commands and adjusting the patrol-read operation accordingly (switching to second mode), the controller mediates the potential conflict between data integrity checking and host-read processing, reducing latency impact.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Reliability

If a comprehensive patrol-read operation is executed, then data integrity is improved, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoidpatrol-read operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the patrol-read operation into two distinct modes (first mode for comprehensive reading, second mode for reduced reading) that can be selectively executed. This segmentation simplifies the overall control logic by providing clear decision points based on host-read command presence, rather than implementing a single complex adaptive algorithm.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12086429B2Memory system and controlling method
Publication Date: 2024.09.10 KIOXIA CORP
  • US12086429B2 patent drawing
  • US12086429B2 patent drawing
  • US12086429B2 patent drawing

AI summary

According to one embodiment, the controller periodically executes a first operation. The controller selects a first mode or a second mode in the first operation. In a case where the first mode is selected, the controller reads pieces of data that are stored in contiguous memory locations, respectively, that are included in a first physical page or a second physical page. The first physical page is included in a first physical block of a first die. The second physical page is included in a second physical block of a second die. In a case where the second mode is selected, the controller reads first data stored in one memory location of the first physical page and second data stored in one memory location of the second physical page.