Dual-Mode Phase Detector for Fast DLL Lock Without Phase Error
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Solution Overview
Problem
Existing delay-lock loops face challenges in achieving a rapid lock condition without introducing phase errors due to differences in duty cycles between reference and feedback signals.
Innovation Solution
A dual mode phase detector is introduced, comprising a single edge phase detector and a dual edge phase detector, where the dual edge phase detector is used to quickly achieve lock and the single edge phase detector maintains phase alignment to prevent fixed phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a dual edge phase detector is used to quickly achieve lock, then the lock acquisition time is reduced, but phase errors are introduced due to duty cycle differences between reference and feedback signals
Solution Approach 1:
The phase detector is divided into two separate detectors: a dual-edge phase detector for rapid lock acquisition and a single-edge phase detector for maintaining accurate phase alignment. This segmentation allows each detector to be optimized for its specific function, resolving the contradiction between fast locking and phase accuracy.
Solution Approach 2:
The system dynamically switches between two operational modes: during the acquisition phase, the dual-edge detector is active for fast locking; once locked, the single-edge detector takes over for precise phase maintenance. This dynamic switching resolves the contradiction by adapting the detector type to the current operational state.
2Measurement precision
If a single edge phase detector is used to maintain phase alignment, then phase accuracy is improved, but the lock acquisition time increases
Solution Approach 1:
The phase detection function is segmented into two specialized detectors: one optimized for speed (dual-edge) and one optimized for accuracy (single-edge). This allows the system to use the appropriate detector for each phase of operation, avoiding the compromise of using a single detector type for both purposes.
Solution Approach 2:
The dual-edge detector performs the preliminary action of rapid lock acquisition, getting the system quickly into the locked state. Once this preliminary goal is achieved, the single-edge detector takes over for ongoing precise phase maintenance, eliminating the need for the accurate detector to work slowly during acquisition.
3Ease of operation
If a delay-lock loop is used to control timing of periodic signals, then timing control is achieved, but the loop takes excessive time to achieve locked condition
Solution Approach 1:
The phase detector within the delay-lock loop dynamically adapts its operation mode based on the locking state. During acquisition, it operates in dual-edge mode for maximum speed; after locking, it switches to single-edge mode for precision. This dynamic behavior allows the DPLL to achieve both fast lock time and accurate timing control.
Solution Approach 2:
The system changes the operational parameters of the phase detector based on the locking state. The detector transitions from a high-speed configuration (dual-edge detection) during acquisition to a high-precision configuration (single-edge detection) during steady-state operation, optimizing performance for each phase.
Data Source
AI summary
A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals indicative of the phase relationship between the rising edge of a reference signal and the rising edge of a feedback signal generated by the delay-lock loop. The dual mode phase detector also includes a dual edge phase detector that generates output signals indicative of the phase relationship between both the rising edge of a reference signal and the rising edge of the feedback signal and the falling edge of a reference signal and the falling edge of the feedback signal. A lock detector controls a switch so that it couples the output signals from the single edge phase detector to a delay line when the loop is locked, and it otherwise couples the output signals from the dual edge phase detector to the delay line.