Dual-Mode Pixel Layout With RDTI for EVS-Image Interference
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Solution Overview
Problem
Current image sensors face challenges in simultaneously supporting event-based vision sensor (EVS) and image capture modes due to inter-mode interference and spatial overlap of metal wirings, which affects the quality of both EVS and image-frame-capture modes.
Innovation Solution
The design incorporates a pixel unit cell with both EVS and imaging pixels, where transistors are arranged along boundary regions formed by rear deep trench isolation (RDTI), optimizing wiring and maximizing photodiode areas, and allowing for simultaneous readout of event and image signals without switch gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If EVS and imaging pixels are integrated in the same sensor, then the sensor can simultaneously support event-based vision and image capture modes, but inter-mode interference and spatial overlap of metal wirings occur which degrades signal quality
Solution Approach 1:
The sensor is divided into distinct pixel types (EVS pixels and imaging pixels) with separate readout circuits and signal processing paths. EVS pixels use asynchronous event-based readout while imaging pixels use frame-based readout, allowing independent operation without mutual interference. The pixel array is segmented into functional zones that can be activated independently based on operating mode requirements.
Solution Approach 2:
The harmful spatial overlap of metal wirings is eliminated by extracting and redistributing interconnect routes. Different metal layers are assigned to different pixel types: upper metal layers serve imaging pixels while lower metal layers serve EVS pixels. This separation removes the source of inter-mode interference and allows each pixel type to operate with optimal wiring configurations.
2Ease of manufacture
If transistors are placed in the same layer for both EVS and imaging pixels, then manufacturing is simplified, but transistor density increases which reduces available photodiode area
Solution Approach 1:
Transistors are moved from the planar pixel area into the vertical dimension by placing them in deep trench isolation regions below the photodiode level. This three-dimensional arrangement allows photodiodes to occupy the full pixel area while transistors are accommodated in the vertical space within the trench structures, effectively adding a depth dimension to the layout and eliminating the area trade-off.
Solution Approach 2:
Transistors are nested within the deep trench isolation structures that already exist for pixel separation. The trench regions, which would otherwise be wasted space, are utilized to house transistor components. This nesting approach allows dual-layer transistor integration where imaging pixel transistors and EVS pixel transistors share the same vertical space without increasing lateral footprint.
3Productivity
If separate readout circuits are provided for EVS and imaging pixels, then simultaneous readout is enabled, but device complexity and wiring requirements increase
Solution Approach 1:
Shared circuit blocks are designed to handle both EVS and imaging pixel signals through configurable multiplexing. Column signal processing circuits can be dynamically assigned to process either EVS asynchronous events or imaging frame data based on the active operating mode. This multi-functional approach enables simultaneous readout capability while reducing the total number of dedicated circuits needed.
Solution Approach 2:
The readout system employs dynamic mode switching that allows flexible allocation of readout resources. Control logic dynamically configures signal routing and processing parameters based on whether EVS mode, imaging mode, or dual-mode operation is active. This dynamic adaptability allows the system to optimize circuit utilization in real-time without requiring fully static dedicated circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces inter-mode interference, enhances EVS sensitivity, and maintains larger active photodiode areas, resulting in improved image quality and event detection capabilities.
Implementation Method 1
The EVS and imaging pixels are configured to include event sensing and imaging pixel transistors formed in the same transistor layer of an integrated circuit assembly that also includes the photodiodes
Data Source
AI summary
Image sensing devices are disclosed. In one example, an image sensing device includes a pixel unit cell with both event sensing (EVS) pixels and imaging pixels. The EVS and imaging pixels are configured to include event sensing and imaging pixel transistors formed in the same transistor layer of an integrated circuit assembly that also includes the photodiodes of the EVS and imaging pixels. The photodiodes are separated by a rear deep trench isolation (RDTI), and the EVS and imaging pixel transistors are arranged along (e.g., underneath) boundary areas formed by the RDTI, maximizing the space available for the photodiodes and economizing on wiring requirements for the EVS and imaging pixels.