Dual-Mode PLL Oscillator Control for Low-Power Stable Clocks
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Solution Overview
Problem
Phase-locked loops (PLLs) in communication systems face challenges in achieving low power consumption and high immunity to voltage and temperature variations, particularly in computationally-intensive applications like artificial intelligence and IoT, while also requiring efficient circuit area usage and reduced manufacturing costs.
Innovation Solution
A phase-locked loop circuit employing a hybrid control scheme with a hybrid phase frequency detector (PFD) circuit and a hybrid oscillator circuit, utilizing a digital code generator and frequency divider to adjust the output clock frequency based on both analog and digital control signals, enabling a dual mode operation that includes a free-running digitally controlled oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL circuit is used, then clock synchronization and frequency synthesis can be achieved, but power consumption increases and immunity to voltage and temperature variations decreases
Solution Approach 1:
The patent implements a dual-mode oscillator that can dynamically switch between analog control mode and digital control mode. The analog mode provides high immunity to voltage and temperature variations, while the digital mode reduces power consumption. This dynamic adaptability allows the system to optimize performance based on operating conditions, resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The patent changes the control parameter type from purely analog to a hybrid analog-digital system. By introducing digital control codes that can selectively override analog control, the system achieves lower power consumption in digital mode while maintaining the high immunity characteristics of analog control when needed, thus resolving the contradiction between power consumption and immunity to variations.
2Reliability
If a dual mode PLL circuit is implemented, then power consumption is reduced and immunity is improved, but circuit area increases
Solution Approach 1:
The patent designs the oscillator to serve multiple functions: it can operate in analog control mode for high immunity requirements, digital control mode for low power consumption requirements, and hybrid mode for balanced performance. This multi-functionality allows a single circuit implementation to address multiple operating scenarios, reducing the need for separate dedicated circuits and thereby minimizing overall circuit area while maintaining high immunity capabilities.
3Use of energy by moving object
If digital control is used in oscillator, then power consumption is reduced, but immunity to voltage and temperature variations decreases
Solution Approach 1:
The patent implements dynamic mode switching capability where the oscillator can transition between analog control mode (high immunity) and digital control mode (low power consumption) based on system requirements. This dynamic adaptability resolves the contradiction by allowing the system to use digital control when power consumption is the priority while switching to analog control when immunity to variations is more critical.
Solution Approach 2:
The patent segments the control mechanism into two independent control paths: analog control path and digital control path. Each path can be independently activated or deactivated based on operational requirements. The analog path maintains high immunity characteristics, while the digital path reduces power consumption, allowing the system to segment the control functions to resolve the contradiction between power consumption and immunity.
Data Source
AI summary
A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.