Dual-Mode PLL for Low-Power IoT with Jitter Reduction
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Solution Overview
Problem
Existing PLL systems for IoT devices face challenges in achieving low-power consumption and low-jitter noise, which are crucial for extended battery life and reliable operation.
Innovation Solution
A dual-mode, low-power, low-jitter phased locked loop (PLL) system is designed with a voltage-controlled oscillator, a phase frequency detector, a programmable charge pump circuit, and a tunable loop filter circuit, allowing operation in different wireless protocols like Bluetooth and Wi-Fi, with adjustable bandwidth to maintain constant power consumption and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a PLL system is designed for low-power consumption, then battery life is extended, but jitter noise increases
Solution Approach 1:
The patent implements a dual-mode PLL system that dynamically switches between wide-band and narrow-band operational modes. The wide-band mode provides fast acquisition and low power consumption, while the narrow-band mode provides low jitter noise. This dynamic adaptation allows the system to optimize between power consumption and noise performance based on operational requirements.
Solution Approach 2:
The system changes key parameters (bandwidth, charge pump current, loop filter coefficients) to transition between operational modes. By adjusting these parameters, the PLL can achieve low-power operation with acceptable jitter performance, resolving the contradiction between power consumption and jitter noise.
2Object-affected harmful factors
If the PLL bandwidth is increased to reduce jitter noise, then noise performance improves, but power consumption increases
Solution Approach 1:
The patent employs dynamic bandwidth adjustment where the PLL operates in wide-band mode during frequency acquisition and in narrow-band mode during steady-state operation. This dynamic switching allows the system to achieve low jitter noise only when necessary, thereby reducing overall power consumption while maintaining acceptable noise performance.
3Speed
If the PLL is designed for fast frequency acquisition, then lock time is reduced, but jitter noise increases
Solution Approach 1:
The patent implements a two-stage acquisition process: first using wide-band mode for rapid frequency acquisition, then transitioning to narrow-band mode for jitter reduction. This periodic switching between operational modes allows the system to achieve both fast lock time and low jitter noise at different stages of operation.
Data Source
AI summary
A Dual-mode forward path PLL system and method are disclosed. The forward path PLL system includes a phase frequency detector (PFD) circuit including a first input node a second input node, a first output node a second output node, where the PFD receives a first input signal, a second input signal and generates a first output signal and second output signal, and where the first input signal is a reference frequency signal and the second input signal is a divided frequency value signal, a charge pump circuit including a third input node, a fourth input node and a third output node, where the third input node and the fourth input node are coupled to the first output node and the second output node of the PFD and where the Charge pump is programmable; and a loop filter circuit including a fifth input node and fourth output node, where the fifth input node is coupled to the third output node of the charge pump and where the loop filter circuit is programmable. In some aspects, the up-side switch and the down-side switch are current sources and the divided frequency value is signal is a fractional frequency value signal.