Dual-Mode PLL Clock Generation for Low-Jitter Frequency Control
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Solution Overview
Problem
Existing PLL implementations face challenges in meeting stricter specifications due to process, voltage, and temperature variations, particularly in reducing jitter propagation from the reference clock signal to the PLL output clock signal in high-speed communication protocols.
Innovation Solution
A clock generation circuit utilizing dual-mode PLLs that can operate in integer-N or fractional-N modes, combined with a 2-to-1 multiplexer and control logic to switch between reference clocks, allowing for finer frequency control and improved jitter reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If adjustment circuits are added to tune PLL parameters, then frequency control capability is improved, but jitter propagation increases due to process, voltage, and temperature variations
Solution Approach 1:
The patent divides the reference clocking system into multiple independent reference clocks (first reference clock and second reference clock) with different frequencies. Each reference clock feeds into separate PLL circuits, allowing independent optimization and selection to minimize jitter propagation while maintaining frequency control capability.
Solution Approach 2:
The patent employs multiple reference clocks with different frequency parameters (first reference clock frequency and second reference clock frequency) to allow the system to select optimal parameters under different operating conditions, thereby reducing jitter propagation while maintaining ease of frequency control.
2Object-affected harmful factors
If multiple PLL circuits are used with different reference clocks, then jitter reduction is improved, but device complexity increases
Solution Approach 1:
The patent designs PLL circuits that can operate with multiple reference clock inputs, making each PLL multi-functional. The same PLL circuitry can accept either the first reference clock or the second reference clock, reducing overall device complexity while maintaining jitter reduction capabilities through selective reference clock usage.
Data Source
AI summary
A clock generation circuit arranged in a first system is disclosed. The clock generation circuit includes: a first dual-mode PLL, arranged for generating a first output clock in an integer-N mode or a fractional-N mode selectively, the first output clock being generated based on a first reference clock; and a second dual-mode PLL, arranged for generating a second output clock in an integer-N mode or a fractional-N mode selectively, the second output clock being generated based on the first output clock or a second reference clock selectively. Associated circuitries are also disclosed.