Dual-Mode PLL Oscillator Control for Low-Power Stable Clocks
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits face challenges in achieving low power consumption and high immunity against voltage and temperature variations, particularly in computationally-intensive applications.
Innovation Solution
The proposed PLL circuit employs a hybrid control scheme using a hybrid phase frequency detector (PFD) circuit and a hybrid oscillator circuit, which allows for dual mode operation, including a free-running digitally controlled oscillator mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional PLL circuit is used, then clock synchronization and frequency synthesis can be achieved, but power consumption increases and immunity against voltage and temperature variations decreases
Solution Approach 1:
The patent implements dual-mode operation where the oscillator circuit can dynamically switch between PLL mode (with PFD circuit active) and free-running oscillator mode (with PFD circuit inactive). This dynamic configuration allows the system to adapt power consumption and reliability characteristics based on operational requirements, achieving low power consumption while maintaining immunity against environmental variations through the free-running mode.
2Use of energy by moving object
If a hybrid control scheme is implemented, then power consumption is reduced and immunity is maintained, but circuit complexity increases
Solution Approach 1:
The oscillator circuit is designed with multi-functionality to operate in both PLL mode and free-running oscillator mode using the same hardware components. The PFD circuit and oscillator circuit share common elements, allowing the system to achieve low power consumption and high immunity without requiring completely separate circuit implementations for each mode, thereby limiting the increase in circuit complexity.
3Area of stationary object
If dual mode operation is enabled, then power consumption is reduced and circuit area is saved, but control complexity increases
Solution Approach 1:
The patent merges the PLL control functionality and free-running oscillator functionality into a single integrated oscillator circuit design. By combining the PFD circuit and oscillator circuit with shared components, the system achieves circuit area savings while the control complexity is managed through unified circuit architecture rather than separate independent circuits.
Data Source
AI summary
A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.