Dual-Mode PMOS N-Well Switching Under Thin-Oxide Voltage Stress
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Solution Overview
Problem
In high-density integrated circuits, PMOS transistors face latchup issues due to forward-biased p-n junctions, which can lead to short circuits and damage, especially in modern process nodes where transistor dimensions are reduced and gate oxides are thin, making it challenging to tie n-wells to high-voltage supplies without stressing the transistors.
Innovation Solution
An n-well voltage switching circuit controls the voltage for dual-mode PMOS transistors, biasing the n-well to a high voltage during high-voltage mode and a low voltage during low-voltage mode to prevent latchup, allowing for smaller transistor sizes and thinner gate oxides while ensuring the transistors are not damaged by the high voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the n-well is tied to high-voltage supply to prevent latchup, then latchup is prevented, but the transistor experiences stress and damage due to thin gate oxide and small dimensions
Solution Approach 1:
The patent applies dynamics by making the n-well voltage configuration changeable over time. The n-well is connected to high-voltage supply only during high-voltage mode operation and disconnected during low-voltage mode, transforming a static configuration into a dynamic one that adapts to operational requirements, thus preventing latchup when needed while avoiding stress when not needed
Solution Approach 2:
The patent changes the voltage parameter of the n-well dynamically based on operational mode. During high-voltage mode, the n-well is biased to high voltage to prevent latchup; during low-voltage mode, the connection is disconnected to eliminate stress on thin gate oxide transistors. This parameter change resolves the contradiction between latchup prevention and transistor protection
2Reliability
If robust PMOS transistors with increased dimensions are used to prevent latchup, then latchup is prevented, but die area increases significantly
Solution Approach 1:
The patent enables small-dimension transistors to be used by making the n-well voltage configuration dynamic. During high-voltage mode, the n-well is connected to high-voltage supply to prevent latchup even with small transistors. During low-voltage mode, the connection is disconnected to protect thin gate oxide transistors. This allows modern small-dimension transistors to be used without requiring robust large-dimension transistors
Solution Approach 2:
The patent changes the operational parameters (voltage mode and timing) to enable the use of small-dimension transistors. By controlling when the n-well is connected to high voltage based on operational mode, the patent allows modern small transistors with thin gate oxide to function reliably without requiring the large die area of robust transistors
3Productivity
If thin gate oxide and small transistor dimensions are used to enhance density, then circuit density increases, but the transistor cannot withstand high-voltage stress
Solution Approach 1:
The patent makes the high-voltage stress condition dynamic by controlling the connection between n-well and high-voltage supply based on operational mode. During low-voltage mode, the n-well connection is disconnected to protect thin gate oxide transistors from high-voltage stress. During high-voltage mode, the connection is established to enable high-voltage operation. This dynamic control allows thin gate oxide transistors to be used for high density while protecting them from damaging stress
Solution Approach 2:
The patent changes the voltage parameter dynamically to enable thin gate oxide transistors to operate at high density without damage. By switching the n-well connection state based on operational mode, the patent allows transistors to experience high voltage only when necessary for high-voltage mode operation, while protecting them during low-voltage mode, thus enabling the use of small dimensions for enhanced density
Data Source
AI summary
A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.