Dual Mode Hardware Reset for Storage Wake-Up Latency
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Solution Overview
Problem
Modern host systems face challenges in power management during deep sleep modes, where traditional re-initialization methods are time-consuming, limiting power savings and increasing wake-up latency due to the need for full re-initialization of storage systems.
Innovation Solution
Incorporating a control bit in the storage system that allows for a modified reset mode, enabling faster re-initialization by retaining some power states during deep sleep, reducing the need for full re-initialization upon waking, and allowing for dual reset behaviors controlled by the host device and storage system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional full re-initialization is performed when transitioning from deep sleep mode to operational mode, then system reliability is ensured, but wake-up latency increases and power savings are reduced
Solution Approach 1:
The patent implements partial re-initialization by selectively resetting only critical subsystems (such as the memory controller or interface circuitry) while leaving non-critical subsystems in their current state. This approach ensures system reliability by resetting essential components while avoiding the time penalty of fully re-initializing the entire storage system, thereby reducing wake-up latency from deep sleep mode.
Solution Approach 2:
The storage system is divided into multiple independent subsystems (e.g., memory arrays, memory controller, interface circuitry, power management units). During wake-up from deep sleep, only specific segmented subsystems that require re-initialization are reset, while others remain operational. This segmentation enables selective re-initialization, balancing reliability requirements with reduced wake-up time.
2Reliability
If traditional full re-initialization is performed when transitioning from deep sleep mode to operational mode, then system stability is maintained, but power savings are reduced
Solution Approach 1:
The patent applies partial re-initialization to reset only the minimum necessary subsystems required for stable operation after wake-up, rather than fully re-initializing the entire system. This reduces the energy consumed during the wake-up transition while maintaining system stability through selective resetting of critical components.
Solution Approach 2:
The system performs preliminary assessments during deep sleep mode to identify which subsystems require re-initialization upon wake-up. By pre-determining the re-initialization scope, the system avoids unnecessary power consumption associated with full re-initialization while ensuring that essential subsystems are properly reset for stable operation.
3Adaptability or versatility
If control bit is added to enable dual reset modes, then flexibility and adaptability are improved, but device complexity increases
Solution Approach 1:
The control bit serves multiple functions: it indicates the desired reset behavior (full or partial), communicates between host and storage system, and determines power state retention preferences. This single control bit provides universal control over dual reset modes, achieving high adaptability without proportionally increasing device complexity.
Data Source
AI summary
Systems and methods are disclosed, including selectively providing one of a first reset or a second reset to transition to a storage system from a low power mode to an operational power mode in response to a hardware reset signal and a value of a control bit on the storage system.