Dual Mode Sample and Hold Circuit for ADC Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cyclic pipeline analog to digital converters face challenges in achieving high precision and noise immunity due to inherent errors in capacitors and resistors, limiting precision to 10 bits and being sensitive to noise, especially when dealing with single-end signals.
Innovation Solution
A dual mode sample and hold circuit combining charge-redistribution and flip-around modes, allowing for both single-end and differential signal handling, reduces errors and noise sensitivity by transferring charge in charge-redistribution mode and flipping around in flip-around mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If charge-redistribution mode is used with single-end signals, then input common range is increased, but capacitor matching error accumulates causing significant DNL and INL
Solution Approach 1:
The patent segments the sample and hold operation into two distinct modes: charge-redistribution mode for sampling single-end signals and flip-around mode for holding/differential conversion. This segmentation allows each mode to optimize for its specific function, preventing error accumulation while maintaining input common range flexibility.
Solution Approach 2:
The sample and hold circuit is designed with multi-functionality to handle both single-end and differential signals through different modes. The same circuit infrastructure supports both charge-redistribution and flip-around operations, making it universally applicable to different signal types without requiring separate dedicated circuits for each mode.
2Manufacturing precision
If flip-around mode is used with differential signals, then capacitor matching errors are reduced and noise is cut off, but input common range variation causes output common range errors
Solution Approach 1:
The patent implements dynamic switching between charge-redistribution mode and flip-around mode based on signal type requirements. The circuit can adapt its operating mode in real-time, being dynamic rather than static, allowing optimal performance for both single-end and differential signals without compromise.
Solution Approach 2:
The patent changes the operational parameters of the sample and hold circuit by switching between two distinct modes with different characteristics. Charge-redistribution mode parameters optimize for single-end signal handling while flip-around mode parameters optimize for differential signal processing, allowing parameter adaptation to match signal requirements.
3Area of stationary object
If single-end signals are used, then area and power consumption are reduced, but noise sensitivity increases
Solution Approach 1:
The patent introduces a dual-mode sample and hold circuit as an intermediary between the single-end input signal and the subsequent differential processing stages. This intermediary converts single-end signals to differential form internally, providing noise immunity without requiring the entire system to use differential signaling, thus maintaining area efficiency while reducing noise sensitivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of analog to digital converters by reducing differential and integral nonlinearity, and increasing the signal-to-noise distortion ratio (SNDR), making the circuit more robust and accurate.
Implementation Method 1
signals are stored in sampling capacitors Cs when a sampling signal Φ1 is high and a holding signal Φ2 is low
Implementation Method 2
the charge stored in the sampling capacitors Cs is transferred to a hold capacitor Cf when sampling signal Φ1 is low and holding signal Φ2 is high
Data Source
AI summary
A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential output signal pair and a digital multiplying word and generates the first and second feedback voltages. The sub-ADC receives the differential output signal pair and generates the digital multiplying word and a digital output word. The decoder converts the digital output word to a digital output corresponding to the first and second input voltages.