Dual-Mode Semiconductor Logic Chip for WIO2 and HBM Compatibility
Solution Overview
Problem
The development of semiconductor devices for Wide I/O 2 (WIO2) and High Bandwidth Memory (HBM) is hindered by their distinct chip designs, leading to increased time and cost due to separate manufacturing processes.
Innovation Solution
A semiconductor device is designed with a logic chip and memory chip stacked together, featuring internal and external input/output circuit units compatible with both WIO2 and HBM standards, allowing operation in multiple modes to accommodate different memory types, with through electrodes and mode setting units for signal exchange and mode switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate chip designs are used for WIO2 and HBM, then each memory type can be optimized for its specific interface standard, but development time and cost increase due to separate manufacturing processes
Solution Approach 1:
The logic chip is designed with dual external input/output circuit units (first EIO circuit unit with first EIO pads and second EIO circuit unit with second EIO pads) that can operate in different modes. A mode setting unit (such as a fuse or register) allows the same physical device to be configured for either WIO2 interface standard (using first EIO pads) or HBM interface standard (using second EIO pads), enabling one chip design to serve multiple memory interface purposes without requiring separate manufacturing processes
2Reliability
If separate chip designs are used for WIO2 and HBM, then each memory type can be optimized for its specific interface standard, but manufacturing cost increases due to separate production
Solution Approach 1:
The logic chip incorporates both first and second external input/output circuit units with respective EIO pads that conform to different interface standards. Through the mode setting unit, a single manufactured chip can be configured for WIO2 or HBM applications, eliminating the need for separate production lines and reducing manufacturing costs while maintaining interface compatibility for both memory types
3Ease of manufacture
If a single device supports multiple modes, then development cost decreases, but device complexity increases due to multiple circuit units and mode switching mechanisms
Solution Approach 1:
The logic chip integrates first and second external input/output circuit units with respective EIO pads and a mode setting unit. The mode setting unit (fuse or register) stores configuration information that determines which EIO circuit unit is activated. This approach increases internal circuit complexity but reduces overall system complexity by eliminating the need for separate chips for WIO2 and HBM applications
Solution Approach 2:
The device employs dynamic mode switching where the mode setting unit configures the logic chip to operate in either WIO2 mode (activating first EIO circuit unit) or HBM mode (activating second EIO circuit unit). This dynamic reconfiguration allows the same physical hardware to adapt its functionality based on the required interface standard, managing complexity through software/firmware control rather than requiring multiple fixed designs
Data Source
AI summary
A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.