Dual Mode Source Driving Circuit for LCD Panel
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Solution Overview
Problem
Conventional LCD devices require distinct data register structures for cascade and dual gate modes, leading to increased chip size due to the need for larger multiplexers and routing circuits in dual gate mode operations.
Innovation Solution
A driving circuit capable of operating in both cascade and dual gate modes, featuring a control circuit that generates a source output enable signal with varying pulses during horizontal scanning, allowing the same source driving IC to generate source and gate driving signals based on mode signals, thereby reducing the complexity and size of the chip layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional source driving circuit uses a multiplexer and routing circuit to generate the same number of source driving signals in dual gate mode as in cascade mode, then the number of source driving signals is maintained, but the chip size increases
Solution Approach 1:
The source driving circuit is designed to perform multiple functions by generating different numbers of source driving signals based on the operation mode. The same circuit structure can operate in cascade mode (generating N signals) or dual gate mode (generating 2N signals) without requiring separate dedicated circuits, thereby avoiding the need for additional multiplexers and routing circuits that would increase chip size.
Solution Approach 2:
The circuit employs dynamic control through a mode selection signal that enables the source driving circuit to adapt its output based on operational requirements. By dynamically switching between generating N signals or 2N signals, the circuit maintains versatility without requiring static additional components, thus reducing chip area while preserving productivity.
2Adaptability or versatility
If distinct data register structures are used for cascade mode and dual gate mode, then each mode can be optimized, but the device complexity increases
Solution Approach 1:
A single unified data register structure is designed to serve both cascade mode and dual gate mode operations. The same data register generates source driving signals in cascade mode and generates both first and second source driving signals in dual gate mode, eliminating the need for separate distinct data register structures while maintaining mode-specific functionality through dynamic control.
3Adaptability or versatility
If the source driving circuit is designed to generate twice the number of source driving signals in dual gate mode using additional multiplexer and routing circuit, then the dual gate mode operation is enabled, but the layout size on chip increases
Solution Approach 1:
The source driving circuit is designed as a universal structure that can generate N source driving signals in cascade mode or 2N signals in dual gate mode without requiring additional dedicated multiplexers and routing circuits. The same circuit components are dynamically configured to serve different functions based on the mode selection signal, thereby enabling dual gate mode capability while minimizing layout size.
Data Source
AI summary
The display device includes a driving circuit and a panel. The driving circuit is configured to generate a source output enable signal having at least one pulse during one horizontal scanning period in response to a mode signal and configured to generate a source driving signal by latching an image data in response to the source output enable signal. The driving circuit is further configured to generate an internal horizontal synchronization signal in response to the source output enable signal and configured to generate a gate driving signal in response to the internal horizontal synchronization signal. The panel is configured to display the image data in response to the gate driving signal and the source driving signal.