Dual-mode transistor assist gate mode switching
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Solution Overview
Problem
Current CMOS transistors face limitations in flexibility due to their n-channel and p-channel mode configurations, leading to suboptimal subthreshold slope, transition times, and leakage current, which complicates integrated circuit design and memory operations, especially in flash memory technologies requiring block erase operations.
Innovation Solution
A dual-mode transistor structure capable of operating in both n-channel and p-channel modes with a super steep subthreshold slope, featuring a semiconductor body with p-type and n-type terminal regions, assist gates, and a back gate, allowing for dynamic mode switching between n-channel and p-channel modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CMOS transistor structures are used with fixed n-channel or p-channel mode, then manufacturing is simplified, but flexibility in integrated circuit layout and operation is limited
Solution Approach 1:
The transistor structure enables dynamic switching between n-channel and p-channel modes through assist gates that can induce different carrier populations in the channel region. This dynamic reconfigurability allows the same physical structure to adapt to different circuit requirements, resolving the contradiction between flexibility and complexity.
Solution Approach 2:
The transistor device is designed to perform multiple functions by supporting both n-channel and p-channel operation modes within a single structure. The assist gate mechanism enables the device to function as either an n-channel or p-channel transistor depending on bias conditions, eliminating the need for separate dedicated structures and improving layout flexibility.
2Reliability
If conventional CMOS transistors operate in fixed mode, then device structure is simpler, but subthreshold slope cannot be better than about 60 mV/decade at room temperature
Solution Approach 1:
The assist gate structure dynamically modulates the potential profile in the channel region, enabling super-steep subthreshold slopes that exceed the conventional 60 mV/decade limit. By applying appropriate voltages to the assist gates, the device can achieve steeper switching characteristics while maintaining a relatively simple base transistor structure.
Solution Approach 2:
The assist gates act as intermediary elements that mediate between the main gate control and the channel carrier population. These intermediate control structures enable precise manipulation of the subthreshold behavior without requiring fundamental changes to the core transistor architecture, thus improving reliability while limiting complexity growth.
3Speed
If conventional transistors are used, then leakage current is higher, but transition times are slower
Solution Approach 1:
The dual-mode transistor structure dynamically optimizes the trade-off between transition speed and leakage current by switching between n-channel and p-channel modes. Each mode can be optimized for specific performance requirements, allowing fast transitions when needed while minimizing leakage during standby periods, thus resolving the contradiction between speed and harmful leakage effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-mode transistor structure achieves fast transition times, low leakage current, and efficient operation, enabling improved performance in integrated circuits and memory technologies by allowing for flexible mode switching and efficient data programming and erasing.
Implementation Method 1
For p-channel mode, negative voltages are applied to the assist gates, inducing a population of holes beneath the assist gates to support p-channel mode. For n-channel mode, positive voltages are applied to the assist gates inducing a population of electrons beneath the assist gates to support n-channel mode.
Data Source
Figure 1~3
Figure 4~4B
Figure 5~5A
AI summary
A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.