Dual Module Clock Supply for CAN Communication Modules
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional CAN communication modules face challenges in maintaining bit timing accuracy with frequency jittered clocks, which conflicts with requirements for low electromagnetic interference (EMI) in automotive applications, leading to costly conformance tests and limited bit timing setups.
Innovation Solution
A CAN communication module design with separate clock inputs for the protocol kernel and CAN logic block, utilizing a dual clock generator with a fixed frequency oscillator and frequency modulation phase locked loop to provide low jitter and high frequency clocks respectively, ensuring compliance with CAN standards and minimizing EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a frequency modulated system clock is used to reduce electromagnetic interference, then EMI is minimized, but bit timing accuracy deteriorates due to frequency jitter exceeding the 1.5% limit
Solution Approach 1:
The CAN communication module is divided into two independent parts with separate clock inputs: the protocol kernel receives a stable low-jitter clock for bit timing, while the CAN logic block receives a frequency modulated clock for EMI reduction. This segmentation allows each part to operate with optimal clock characteristics without interfering with the other.
Solution Approach 2:
Different parts of the system are provided with different clock qualities tailored to their specific requirements. The protocol kernel receives a high-quality stable clock for precise bit timing operations, while the CAN logic block receives a frequency modulated clock for EMI mitigation, allowing each component to operate with the appropriate clock characteristics.
2Manufacturing precision
If a stable low jitter clock is used for the entire module, then bit timing accuracy is maintained, but electromagnetic interference increases due to concentrated frequency spectrum
Solution Approach 1:
The system separates the clock distribution into two independent paths: one dedicated to the protocol kernel with stable clock for timing accuracy, and another dedicated to the CAN logic block with frequency modulated clock for EMI reduction. This eliminates the need to choose between stability and EMI performance.
Solution Approach 2:
The stable clock is applied locally to the protocol kernel where timing precision is critical, while the frequency modulated clock is applied locally to the CAN logic block where EMI reduction is the priority, optimizing both aspects simultaneously.
3Manufacturing precision
If separate clock inputs are provided for protocol kernel and CAN logic block, then both bit timing accuracy and EMI reduction are achieved, but device complexity increases
Solution Approach 1:
The phase-locked loop circuit serves multiple functions: it generates the base clock signal, applies frequency modulation for EMI reduction, and distributes clock signals to different parts of the system with appropriate characteristics. This multi-functionality reduces the need for separate clock generation circuits.
Solution Approach 2:
The phase-locked loop acts as an intermediary between the oscillator and the clock consumers, transforming a single stable clock signal into multiple clock signals with different characteristics (stable and frequency modulated), simplifying the overall clock distribution architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for compliant CAN communication modules with reduced EMI and negligible increase in module size, enabling high performance features while minimizing conformance test expenses and maintaining bit timing accuracy.
Implementation Method 1
a frequency modulation phase locked loop circuit (PLL) with a reference input receiving the low jitter clock signal
Implementation Method 2
The frequency modulation PLL provides a logic clock signal which may have a frequency that is a multiple of the low jitter clock signal
Data Source
AI summary
A CAN communication module (10) comprising a protocol kernel (14) and a CAN logic block (12) is provided. The protocol kernel includes a CAN bus interface and the CAN logic block includes a module interface for connection to an external peripheral bus (22), a message RAM (28) and a CAN message handler (26). The protocol kernel (14) and the CAN logic block (12) have separate clock inputs (32,36).