Dual Molded Multi-Chip Package System for IC Density
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Solution Overview
Problem
Current multi-chip packages face challenges in integrated circuit density, assembly process yield, and manufacturing complexity, particularly with vertically stacked circuits, which lead to increased costs and reliability issues due to the inability to test individual integrated circuits before assembly and the use of additional structures that add complexity and potential failure points.
Innovation Solution
A dual molded multi-chip package system is introduced, featuring a first encapsulation around integrated circuit dies and leads, with a semiconductor device mounted over the encapsulation and a second encapsulation covering the system, allowing for improved testing and connection methods without pre-assembling the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional multi-chip packages are pre-assembled before testing, then integrated circuit density increases, but assembly process yield decreases and reliability worsens due to inability to test individual circuits
Solution Approach 1:
The patent applies preliminary action by enabling testing of integrated circuits before they are assembled into the multi-chip package. Individual circuits can be tested and identified as known-good-die (KGD) prior to assembly, allowing defective circuits to be filtered out beforehand. This preliminary testing step improves assembly yield and reliability while maintaining high circuit density.
2Quantity of substance
If vertically stacked integrated circuits are used, then integrated circuit density increases, but manufacturing complexity and cost increase due to difficulty in testing and determining failure modes
Solution Approach 1:
The patent applies segmentation by separating the testing function from the final assembled package. Individual integrated circuits are tested and identified as known-good-die (KGD) before assembly into the vertically stacked multi-chip package. This segmentation allows each circuit to be independently tested and evaluated, simplifying manufacturing processes and reducing complexity while maintaining high density vertical stacking.
3Ease of manufacture
If additional structures such as printed circuit boards, interposers, or flexible wiring are used, then integrated circuits can be connected, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent applies merging by integrating the interconnection function directly into the multi-chip package substrate rather than using separate printed circuit boards, interposers, or flexible wiring. The package substrate itself provides the interconnect structure that electrically connects the vertically stacked integrated circuits, eliminating the need for additional external connection structures and reducing overall device complexity while maintaining manufacturing ease.
Data Source
AI summary
A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.