Dual Molded Stack TSV Package for High I/O Density
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Solution Overview
Problem
The challenge is to integrate a high number of input/output (I/O) pads into increasingly smaller semiconductor die packaging while maintaining a compact form factor, as current technologies face limitations in reducing package dimensions and TSV-induced stress.
Innovation Solution
The solution involves embedding a thinned active die with through silicon vias (TSVs) between redistribution layers (RDLs) to create a system in package (SiP) structure, allowing for reduced package dimensions and increased I/O count, with TSVs having a maximum width of 10 μm or less and a density of at least 2,500 per mm², and RDLs with a maximum thickness of less than 30 μm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the package dimensions are reduced to meet portable device requirements, then the form factor and footprint decrease, but the number of I/O pads that can be integrated is limited
Solution Approach 1:
The patent transitions from planar I/O expansion to vertical stacking by implementing through-silicon vias (TSVs) that penetrate the die substrate. This enables I/O pads to be arranged in multiple vertical layers rather than confined to a single plane, allowing high I/O density within a compact footprint suitable for portable devices
Solution Approach 2:
The patent embeds multiple functional layers within the die structure, including TSVs nested within the substrate, redistribution layers (RDLs) nested between TSV layers, and multiple I/O pad layers nested vertically. This nested architecture maximizes I/O capacity within the constrained package volume
2Quantity of substance
If TSV density is increased to achieve higher I/O count, then more I/O pads can be integrated, but TSV-induced stress increases
Solution Approach 1:
The patent implements a keep-out zone around each TSV where no other TSVs are placed. This local spacing requirement reduces stress concentration and interaction between adjacent TSVs, allowing high overall TSV density while maintaining acceptable stress levels through localized density control
Solution Approach 2:
The patent optimizes TSV geometric parameters including diameter, depth, and spacing to balance density and stress. By controlling TSV aspect ratio and implementing appropriate keep-out zones, the design achieves high I/O density while managing the mechanical stress induced by the TSV array
3Length of stationary object
If the die thickness is reduced to achieve smaller package dimensions, then the form factor decreases, but the structural integrity and routing capacity are compromised
Solution Approach 1:
The patent employs composite structures including multiple RDL layers with different material compositions, TSVs with varied fill materials (copper, tungsten, conductive paste), and encapsulation materials. These composite materials provide both mechanical strength for thin dies and functional routing capacity within the reduced thickness
4Quantity of substance
If more I/O pads are integrated into smaller spaces, then the I/O count increases, but the routing paths become more complex and penalties increase
Solution Approach 1:
The patent utilizes vertical routing through TSVs to connect I/O pads across multiple die layers, replacing complex lateral routing with direct vertical pathways. This dimensional transition simplifies routing topology by establishing direct point-to-point connections through the substrate rather than requiring intricate surface trace networks
Data Source
AI summary
Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick.