Lead-Mounted Dual MOSFET Layout for Lower On-Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to reduce the surface area of semiconductor elements in power semiconductor devices while minimizing the increase in on-resistance, as conventional designs face issues with area reduction and resistance increase due to smaller surface areas.
Innovation Solution
The semiconductor device design includes a first and second semiconductor element with electrodes on opposite surfaces, bonded to leads with insulating layers, allowing for a larger surface area arrangement that reduces on-resistance by mounting elements on opposite surfaces of leads, forming a common drain circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the surface area of semiconductor elements is reduced to enable smaller device footprint, then the device can be mounted in a smaller area, but the on-resistance increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement where semiconductor elements are placed side-by-side on the same surface to a three-dimensional arrangement where elements are mounted on opposite surfaces of a lead. This dimensional change allows both elements to have adequate surface area for low on-resistance while the overall device footprint remains compact, as elements are stacked vertically rather than arranged horizontally.
2Reliability
If multiple semiconductor elements are arranged side by side on the same surface, then electrical connectivity can be established, but the device surface area increases
Solution Approach 1:
Instead of arranging semiconductor elements side-by-side in the same plane, the patent utilizes the third dimension by mounting elements on opposite surfaces of a lead structure. This allows electrical connectivity to be achieved through vertical stacking, reducing the horizontal footprint while maintaining functional connectivity through the lead's conductive structure.
Solution Approach 2:
The patent employs a nested arrangement where semiconductor elements are positioned on opposite surfaces of a central lead structure, with insulating layers and connection structures nested between and around the elements. This nested configuration allows multiple elements to share the same vertical space, reducing overall device area while maintaining electrical connectivity through the shared lead structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a larger surface area for semiconductor elements, reducing on-resistance and allowing for a smaller overall device surface area compared to traditional side-by-side arrangements, while maintaining effective electrical connectivity.
Implementation Method 1
The first semiconductor element and the first lead are bonded to each other with the element reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the element reverse surface of the second semiconductor element facing the lead reverse surface.
Data Source
AI summary
The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.