Dual Multiplication Data Path for Parallel DSP Multiply Scheduling
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Solution Overview
Problem
Digital signal processors face challenges in efficiently processing real-time data streams due to limitations in memory bandwidth and scheduling, particularly in applications requiring predictable non-sequential input patterns.
Innovation Solution
The implementation of a dual multiplication unit architecture in a data path, allowing for parallel execution of single issue multiply instructions, which enhances memory bandwidth and data scheduling through an autonomous streaming engine that manages multiple data streams and supports operations like vector-based finite impulse response filtering and matrix multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single multiplication unit is used in the data path, then the device complexity is low, but the productivity is limited due to sequential execution of multiply instructions
Solution Approach 1:
The multiplication functionality is segmented into two separate multiplication units (first multiplication unit and second multiplication unit) that operate independently in parallel. Each unit handles single issue multiply instructions separately, allowing simultaneous execution of multiple multiply operations without interfering with each other, thus doubling the processing throughput for multiply instructions.
Solution Approach 2:
Two multiplication units are merged into the same data path architecture, sharing common resources such as the data path infrastructure and control logic while maintaining independent execution capabilities. This merging allows the system to achieve higher productivity by executing multiple multiply instructions in parallel within a unified architectural framework.
2Productivity
If memory bandwidth is increased to handle real-time data streams, then the productivity improves, but the device complexity increases due to additional memory controllers and bandwidth management circuits
Solution Approach 1:
Data is pre-loaded into register files before processing begins, and the dual multiplication units are pre-configured to execute multiply instructions in parallel. This preliminary preparation of data and execution units eliminates the need for complex real-time memory bandwidth management during critical processing phases, as the required data is already available in registers.
3Loss of time
If cache memory is added to reduce memory access latency, then the productivity improves, but the device complexity increases due to cache control and management overhead
Solution Approach 1:
Data is pre-loaded into register files from memory before the multiply operations are executed. This preliminary data preparation ensures that all operands are available in fast register storage before the dual multiplication units begin their parallel execution, eliminating the need for complex cache management during the critical multiply operation and reducing memory access latency.
Data Source
AI summary
A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.