Dual Multiply Unit Architecture for Higher Instruction Throughput
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Solution Overview
Problem
Digital signal processors face challenges in efficiently processing real-time data streams due to limitations in memory bandwidth and scheduling, particularly in applications requiring predictable non-sequential input patterns.
Innovation Solution
A processor architecture with dual scalar/vector data paths and an autonomous streaming engine that manages multiple data streams, including support for vector-based operations like finite impulse response filtering, matrix multiplication, and dual issue multiply instructions, to enhance memory bandwidth and data scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors with shared memory are incorporated to improve processing capability, then productivity is improved, but device complexity increases
Solution Approach 1:
The processor is divided into multiple independent multiplication units (first multiplication unit, second multiplication unit) that can operate in parallel. Each unit has its own functional components (multiplier array, carry-save adder circuitry, masking logic) but they share common resources (data paths, memory interfaces), achieving segmentation that improves productivity while managing complexity through modular design
Solution Approach 2:
Multiple multiplication units are merged into a single processor architecture with shared memory resources and interconnected data paths. The first and second multiplication units share the same processor die, memory interfaces, and can access common data registers, combining multiple processing capabilities into one integrated system that improves productivity without proportionally increasing device complexity
2Productivity
If dual issue multiply instructions are implemented to improve throughput, then productivity is improved, but device complexity increases
Solution Approach 1:
The processor performs preliminary setup by configuring the first and second multiplication units with their respective operands before execution. The dual issue multiply instructions are prepared and staged in the instruction pipeline, allowing both multiplication operations to be executed simultaneously in the same clock cycle, improving throughput while managing execution complexity through advance preparation
Solution Approach 2:
The processor transitions from single-issue sequential execution to dual-issue parallel execution by adding a temporal dimension to instruction processing. Two multiplication instructions are issued and executed in parallel across different functional units within the same clock cycle, effectively doubling the instruction throughput without proportionally increasing the complexity of individual instruction execution
3Speed
If carry-save adder circuitry is used to improve multiplication speed, then speed is improved, but device complexity increases
Solution Approach 1:
The carry-save adder circuitry is implemented as separate copies in both the first multiplication unit and the second multiplication unit. Each unit has its own carry-save adder instance that operates independently on its partial products, enabling parallel multiplication operations. This copying approach improves overall processing speed while managing circuit complexity through modular replication of proven circuit designs
Data Source
AI summary
Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication unit. Each of these multiplication units includes carry-save adder circuitry with a respective outputs, partial product alignment multiplexing logic coupled to the outputs of the associated carry-save adder circuitry. The processor further comprises communication paths coupled between the outputs of the carry-save adder circuitry of the first multiplication unit and the partial product alignment multiplexing logic of the second multiplication unit. In other configurations, each of the first and second multiplication units may include one or more instances of masking logic, one or more instances of a multiplier array coupled to the associated instance(s) of masking logic, and one or more instances of a multiplexer set coupled to the associated instance(s) of multiplier array(s). Each of multiplexer set instance(s) of a particular multiplication unit is coupled to the carry-save adder circuitry of that multiplication unit.