Dual Nitride Layer RRAM Structure for Off-Current Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving miniaturization, low power consumption, and high performance while maintaining data storage capabilities, particularly in resistive random access memory (RRAM) devices, due to limitations in the design and fabrication of variable resistance elements.
Innovation Solution
The proposed electronic device includes a semiconductor memory structure with a selector, a first nitride layer, and a second nitride layer, where the selector is formed with a Metal Insulator Transition (MIT) layer or Ovonic Threshold Switch (OTS) material, and the nitride layers are used to enhance the variable resistance pattern's properties, allowing for improved data storage characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single nitride layer is used in the semiconductor memory structure, then the fabrication process is simpler, but the manufacturing precision and reliability of the variable resistance element are insufficient
Solution Approach 1:
The nitride layer is divided into two separate layers: a first nitride layer formed on the sidewalls of the hole, and a second nitride layer formed on the upper portion and sidewalls of the stack. This segmentation allows each layer to perform specific functions independently, improving the precision of the variable resistance element while maintaining manageable structural complexity through modular design
Solution Approach 2:
The patent introduces a vertical stacking dimension by forming the first nitride layer on the hole sidewalls and the second nitride layer on the stack upper portion and sidewalls. This multi-dimensional layering approach enhances the precision control of the variable resistance element by providing separate functional zones in the vertical dimension, rather than relying on a single planar layer
2Length of moving object
If the semiconductor memory device is miniaturized to reduce size, then electronic appliances can be made smaller, but the off-current increases and reliability decreases
Solution Approach 1:
Different regions of the memory structure are assigned different nitride layer configurations: the first nitride layer is localized on the hole sidewalls to control off-current at the interface region, while the second nitride layer is positioned on the stack upper portion and sidewalls to enhance reliability of the variable resistance element. This local quality differentiation allows miniaturization while maintaining reliability through region-specific optimization
Solution Approach 2:
The nitride layers serve as intermediary structures between the conductive elements and the variable resistance pattern. The first nitride layer acts as an intermediary on the hole sidewalls to prevent leakage, while the second nitride layer intermediates between the stack components to enhance stability. These intermediary layers enable miniaturization by providing reliable interfaces at reduced dimensions
3Productivity
If conventional fabrication processes are used for RRAM devices, then the manufacturing process is simpler, but the fabrication process margins are reduced and performance is limited
Solution Approach 1:
The first nitride layer is formed preliminarily on the hole sidewalls before forming the selector and stack structures. This preliminary action establishes precise geometric boundaries and protects the underlying structures during subsequent fabrication steps, increasing fabrication process margins while maintaining efficiency through pre-planned structural preparation
Solution Approach 2:
The patent adds vertical dimensionality by forming nitride layers on sidewalls and upper portions rather than only on planar surfaces. This multi-dimensional approach provides additional fabrication process margins by creating protective and defining structures in the vertical dimension, enabling more precise control during subsequent processing steps without reducing overall productivity
Data Source
AI summary
An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer including a hole over a substrate; a first nitride layer disposed on sidewalls of the hole; a selector disposed in a bottom portion of the hole and over the first nitride layer on the sidewalls of the hole; a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and a second nitride layer disposed in an upper portion and on sidewalls of the stacked structure.