Dual Nonvolatile Memory Storage Device for Latency Optimization
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Solution Overview
Problem
Current NAND flash storage devices face challenges in optimizing performance due to latency differences between various nonvolatile memory cell arrays, which affect data access efficiency and storage system integration.
Innovation Solution
A storage device and system that incorporates a first nonvolatile memory cell array and a second nonvolatile memory cell array, with a memory controller managing mapping tables to selectively store and retrieve data based on access patterns, utilizing a vertically stacked NAND flash memory configuration for the first array and a Single Level Cell (SLC) or other fast-access memory for the second array to minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single type of nonvolatile memory cell array is used, then device complexity is reduced, but data access speed and system performance deteriorate due to latency differences
Solution Approach 1:
The memory system is segmented into two distinct nonvolatile memory cell arrays: a first array for storing original data and a second array for storing frequently accessed data. This segmentation allows each array to be optimized for its specific function, with the second array providing faster access for hot data while the first array maintains overall storage capacity, thereby resolving the contradiction between access speed and system complexity.
Solution Approach 2:
The second nonvolatile memory cell array acts as an intermediary cache between the host system and the first nonvolatile memory cell array. When data access patterns indicate frequent requests for specific data, the system automatically copies this data to the second array, which provides faster access. The memory controller manages this intermediary layer, transparently handling data movement and mapping, thus improving access speed without requiring complex external caching infrastructure.
2Productivity
If data is stored in a single memory array, then storage capacity is maximized, but data access efficiency deteriorates due to uniform latency across all data
Solution Approach 1:
Different regions of the storage system are assigned different quality characteristics: the second nonvolatile memory cell array is optimized for fast access with lower latency, while the first array provides bulk storage capacity. The memory controller dynamically determines which data should reside in which array based on access patterns, ensuring that frequently accessed data enjoys the local quality advantage of faster access while maintaining overall storage efficiency.
Solution Approach 2:
The system dynamically adjusts data placement between the two memory arrays based on observed access patterns. When the memory controller detects that certain data is accessed frequently, it automatically transfers this data to the second array for faster access. This dynamic adaptation allows the system to optimize data access efficiency in real-time, reducing latency for hot data while maintaining comprehensive storage capacity across both arrays.
3Speed
If a cache memory structure is added to improve access performance, then data retrieval speed is improved, but device complexity and management overhead increase
Solution Approach 1:
The system changes the state parameters of existing nonvolatile memory cell arrays to create cache functionality without adding separate cache hardware. By adjusting how the two arrays are organized and managed, and by implementing software-based cache management in the memory controller, the system achieves cache-like performance using parameter changes rather than structural additions, thereby improving retrieval speed while minimizing complexity increases.
Data Source
AI summary
A storage device, a storage system comprising the same, and operating methods of the storage device are provided. The storage device includes a first nonvolatile memory cell array which includes a plurality of cell strings arranged in a direction perpendicular to a substrate, and stores first data at a first address, a second nonvolatile memory cell array which stores second data selected from the first data at a second address, in accordance with an access pattern to the first data, and a memory controller which manages a first mapping table indicating that the second data is stored at the second address of the second nonvolatile memory cell array, and a second mapping table indicating that the first data as original data of the second data is stored at the first address.