Dual-NVM Memory Controller for Real-Time Error Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The evolution of embedded non-volatile memory (e.g., eFlash) has lagged behind microcontroller unit (MCU) process platforms, limiting high-end MCU performance due to slower read and write speeds and reliability issues in new NVM technologies like RRAM, which are susceptible to environmental factors and conventional architectures fail to correct errors beyond ECC capabilities.
Innovation Solution
A memory controller architecture with a first NVM for main memory and a second NVM for backup, coupled with additional memory controllers and bus interfaces, enabling real-time error correction and automatic content repair using backup data from the second NVM to ensure data integrity and continuous system operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If new NVM technologies (RRAM, PCM, MRAM, FeRAM) are used to replace eFlash memory, then read and write speeds are improved, but data reliability deteriorates due to susceptibility to environmental factors and perturbations
Solution Approach 1:
The patent implements a backup NVM that pre-stores correct data before errors occur. When the main NVM experiences data corruption due to environmental factors, the backup NVM immediately provides the correct data for correction, eliminating the need for complex error correction algorithms and enabling real-time reliability restoration.
Solution Approach 2:
The patent creates a duplicate copy of the main NVM data in the backup NVM. This copying mechanism allows the system to maintain an identical replica that can replace corrupted data, effectively decoupling the speed advantages of new NVM from their reliability weaknesses through redundancy.
2Reliability
If conventional NVMC architecture with ECC function is used, then single-bit errors are corrected, but errors exceeding ECC capability cannot be repaired
Solution Approach 1:
The patent segments the error handling function into two parts: the ECC unit handles common single-bit errors efficiently, while the backup NVM handles severe multi-bit errors that exceed ECC capability. This segmentation allows the system to maintain high-speed error correction for typical cases while having a fallback mechanism for exceptional cases.
Solution Approach 2:
The backup NVM acts as an intermediary data source that the NVMC can access when ECC correction fails. The NVMC first attempts ECC correction, and only when that fails does it retrieve data from the backup NVM, creating a hierarchical error handling approach that combines the speed of ECC with the reliability of backup replacement.
3Reliability
If backup NVM and second memory controller are added to the architecture, then data integrity is improved through automatic repair, but device complexity increases
Solution Approach 1:
The patent implements self-service error recovery where the backup NVM automatically provides correction data without external intervention. When data corruption is detected, the NVMC autonomously retrieves correct data from the backup NVM and repairs the main NVM, eliminating the need for manual error handling or complex external correction mechanisms.
Solution Approach 2:
The patent merges the backup storage function with the existing NVMC architecture, integrating the second memory controller and backup NVM into a unified error handling system. This combining approach allows the backup mechanism to work seamlessly with the main NVM through shared control logic, reducing the overhead that would result from completely separate systems.
Data Source
Figure 1~3
Figure 4A~4B
Figure 4C
AI summary
A memory controller and an MCU chip are provided by the present application. The memory controller adds a second memory controller to conventional memory controller architecture and is coupled to second NVM storing a backup of content of first NVM in the memory controller. With this arrangement, one more memory access path is established, which takes full advantage of the fast reading characteristics of the first NVM, and once a system bus identifies an error in content read from the first NVM or a problematic address, the second memory controller can automatically read exactly corresponding backup content from the second NVM and provide it on the system bus, or use it to accurately correct the error in the first NVM. This ensures correctness of content that a central processing unit (CPU) or other master on the system bus reads, without interrupting execution of the system's program.