Dual NVM Memory Cells with Variable Oxide Thickness
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Solution Overview
Problem
Existing non-volatile memory (NVM) cells in semiconductor devices face limitations in data retention and endurance cycling due to thin oxide thicknesses, which are optimized for logic gates and not suitable for applications requiring more stringent data retention and extended endurance.
Innovation Solution
A programmable non-volatile device with a floating gate and a drift region configured for hot channel electron injection, using a high voltage process to achieve capacitive coupling and enhance oxide thickness to at least 100 angstroms, allowing integration into high voltage portions of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If thin oxide thickness is used for NVM cell, then programming efficiency is improved, but data retention and endurance cycling are worsened
Solution Approach 1:
The invention divides the semiconductor device into two distinct memory regions: a first NVM cell array with thin gate oxide optimized for programming speed, and a second NVM cell array with thick gate oxide optimized for data retention and endurance. This segmentation allows each region to be independently optimized for its specific function without compromise.
Solution Approach 2:
Different regions of the memory device are given different oxide thicknesses according to their specific requirements. The first NVM cell array uses thin oxide (65-70 Angstroms) for efficient programming, while the second NVM cell array uses thick oxide (100-150 Angstroms) for robust data retention and endurance, allowing each local region to have the quality it needs.
2Reliability
If thick oxide thickness is used for NVM cell, then data retention and endurance cycling are improved, but programming efficiency is worsened
Solution Approach 1:
The invention divides the semiconductor device into two distinct memory regions: a first NVM cell array with thin gate oxide optimized for programming efficiency, and a second NVM cell array with thick gate oxide optimized for data retention and endurance cycling. This segmentation allows each region to be independently optimized for its specific function without compromise.
Solution Approach 2:
Different regions of the memory device are given different oxide thicknesses according to their specific requirements. The first NVM cell array uses thin oxide (65-70 Angstroms) for efficient programming, while the second NVM cell array uses thick oxide (100-150 Angstroms) for robust data retention and endurance, allowing each local region to have the quality it needs.
3Reliability
If NVM cell is integrated into high voltage process, then data retention is improved, but process complexity is increased
Solution Approach 1:
The invention merges the NVM cell structure with the high voltage transistor structure, using the same gate, source, drain, and drift region for both high voltage switching and memory functions. This integration eliminates the need for separate NVM fabrication processes and allows both functions to be achieved using a single high voltage process flow.
Solution Approach 2:
The high voltage transistor structure serves dual purposes: as a high voltage switch and as a non-volatile memory cell. The gate oxide that provides high voltage breakdown capability also serves as the memory storage medium, allowing the same structure to fulfill multiple functions without requiring additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables robust data retention and extended endurance cycling while maintaining zero or low additional process complexity, allowing NVM cells to be integrated into high voltage portions of semiconductor devices, suitable for both one-time and multiple-time programmable applications.
Implementation Method 1
a drift region coupled to the drain region which overlaps a sufficient portion of said gate such that a programming voltage for the device applied to the first terminal of the drain region and second terminal of the source region can be imparted to the floating gate through areal capacitive coupling
Data Source
AI summary
An integrated circuit includes two different types of embedded memories, with cells that have different retention characteristics, and situated in different areas of the substrate. In some applications the cells are both non-volatile memories sharing a common gate layer but with different oxide layers, different thicknesses, etc. The first type of cell is a conventional flash cell which can be part of a logic/memory region, while the second type of cell uses capacitive coupling and can be located in a high voltage region. Because of their common features, the need for additional masks, manufacturing steps, etc. can be mitigated.