Dual OTP Differential Bit Cell for Fast Read Access

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Solution Overview

Problem

Existing one-time programmable (OTP) bit cells in EPROMs suffer from significant current drop over time due to charge loss from the floating gate, leading to slowed sense amplifier performance and the need for differential sensing, which is either inaccurate or area-intensive.

Innovation Solution

A dual OTP differential bit cell design is introduced, featuring two parallel OTP cells and a MOS transistor, eliminating the need for a reference voltage and maintaining high performance with minimal area increase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If a single-ended OTP bit cell is used, then the area is minimized, but the read access time increases significantly over time due to current drop

Engineering Contradiction:

Improvebit cell areaVSAvoidread access time

Core Design Contradiction:

Area of moving objectVSSpeed

Solution Approach 1:

The invention divides the bit cell into two symmetric OTP cells (first and second OTP cells) that operate differentially. Each OTP cell controls a separate pull-down transistor (first and second pull-down transistors) that drive complementary bit lines. This segmentation allows the circuit to maintain strong drive capability over time by comparing differential signals, resolving the contradiction between minimal area and fast read access time.

Inventive Principle:

Principle #1Segmentation

2Speed

If differential sensing is implemented using two separate bit cells, then the read access time is improved, but the area consumption doubles

Engineering Contradiction:

Improveread access timeVSAvoidbit cell area

Core Design Contradiction:

SpeedVSArea of moving object

Solution Approach 1:

The invention merges two OTP cells and their associated pull-down transistors into a single integrated bit cell structure. The first and second OTP cells share common wiring and are symmetrically arranged, allowing differential sensing to be achieved without duplicating the entire bit cell infrastructure. This merging maintains fast read access time while avoiding the area penalty of using two completely separate bit cells.

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If the OTP cell current drops over time due to charge loss, then the floating gate structure is simple, but the sense amplifier performance degrades

Engineering Contradiction:

Improvefloating gate structureVSAvoidsense amplifier performance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The invention inverts the traditional sensing approach by using pull-down transistors that actively pull the bit lines low when OTP cells are programmed, rather than relying on weak pull-up transistors to detect high impedance states. This inversion creates stronger signal levels that are less susceptible to degradation from charge loss in the floating gate, maintaining sense amplifier performance over time while keeping the floating gate structure simple.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS8324663B2Area efficient high-speed dual one-time programmable differential bit cell

Publication Date: 2012.12.04 TEXAS INSTRUMENTS INC

AI summary

One-time programmable (OTP) Electronically Programmable Read-Only Memories (EPROMs) have been used in a number of applications for many years. One drawback with these OTP EPROMs is that these nonvolatile memories tend to be slow and/or may use a considerable amount of area. Here, however, a bit cell is provided that employs a compact dual cell, which generally includes two OTP cells. These OTP cells are generally arranged in differential configuration to increase speed and are arranged to have a small impact on area.