Dual-Output DAC Architecture With Fewer Switches and Smaller Layout

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Solution Overview

Problem

Conventional digital to analog converters require a large number of switches, leading to a significant layout area occupation, especially in mixed-mode systems where they act as an interface between digital and analog signal processing components.

Innovation Solution

The proposed digital to analog converter architecture reduces the number of switches by utilizing a reference voltage circuit generating (2n+1) reference voltages, with a first and second switch array controlled by the input signal, and a switch circuit that outputs two voltages, where odd and even reference voltages are directly transmitted to respective arrays, minimizing the number of switches required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional digital to analog converter architecture is used, then the converter can accurately convert digital signals to analog signals, but the number of switches required is large (N×2^N+2^N), resulting in large layout area occupation

Engineering Contradiction:
Improvesignal conversion accuracyVSAvoidlayout area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent segments the n-bit input signal into two parts: the first bit controls a first switch array that selects from 2^N reference voltages, while the remaining (n-1) bits control a second switch array that further selects between two voltages. This segmentation reduces the total switch count from N×2^N+2^N to approximately 2^(N+1) switches, significantly reducing layout area while maintaining conversion accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts the most significant bit (first bit) from the input signal to control the first switch array, separating its function from the other bits. This extraction allows the second switch array to handle only (n-1) bits, reducing the number of switches required in the second stage from 2^N to 2^(N-1), thereby reducing overall circuit complexity and layout area.

Inventive Principle:
Principle #2Taking out (Extraction)

2Area of stationary object

If the number of switches is reduced to decrease layout area, then the layout area occupation is reduced, but the converter complexity increases due to the need for multiple switch arrays and reference voltage circuits

Engineering Contradiction:
Improvelayout areaVSAvoidcircuit architecture complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The reference voltage circuit generates 2^N reference voltages that serve multiple purposes: they are used by the first switch array for coarse selection and by the second switch array for fine selection. This multi-functionality eliminates the need for separate voltage generation circuits for each switch array, reducing overall circuit complexity despite the reduced switch count.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The first switch array performs preliminary selection of reference voltages based on the most significant bit before the second switch array performs final selection based on the remaining bits. This preliminary action simplifies the control logic of the second switch array, as it only needs to select between two pre-selected voltages rather than directly selecting from all 2^N reference voltages, thereby reducing overall circuit complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20100328126A1Digital to analog converter
Publication Date: 2010.12.30 HIMAX TECH LTD
  • US20100328126A1 patent drawing
  • US20100328126A1 patent drawing
  • US20100328126A1 patent drawing

AI summary

An embodiment of a digital to analog converter (DAC) with two outputs is provided. The DAC is controlled by an n-bits input signal and comprises a reference voltage circuit generating (2n+1) reference voltages, a first switch array and a second switch array. The first switch array receives and outputs 2n selected reference voltages among the (2n+1) reference voltages to the second switch array. The second switch array outputs a first voltage via a first output terminal and a second voltage via a second output terminal according to the input signal, wherein the (2i+1)th reference voltages are directly transmitted to the second switch array, and when the first bit of the input signal is at a first voltage level, the first voltage is transmitted to the second output terminal, and the second voltage is transmitted to the first output terminal.