Dual-Output Driver Circuit for Compact PMOS-NMOS Pixel Control
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Solution Overview
Problem
Display devices with pixels containing both PMOS and NMOS transistors require separate drivers for outputting and inverted output signals, leading to increased complexity and size.
Innovation Solution
A driver design that includes stages with input circuits for both input and inverted input signals, output circuits for both low and high gate voltages, and transistors that are always-on to manage node separation, allowing simultaneous output of both signals with a reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate drivers are used to output output signals and inverted output signals, then the pixel can receive both signal types, but the driver complexity and size increase
Solution Approach 1:
The patent combines separate output driver circuits into a single integrated driver that outputs both the output signal and inverted output signal simultaneously. The driver includes a first output circuit that outputs the output signal and a second output circuit that outputs the inverted output signal, both controlled by the same clock signal and input signal, thereby reducing structural complexity while maintaining signal output capability.
Solution Approach 2:
The driver circuit is designed with multi-functionality to perform both output signal generation and inverted output signal generation within a single device. The driver uses shared components such as the clock signal input, input signal, and transistor structures to accomplish multiple functions, reducing the overall driver size and complexity compared to using separate dedicated drivers.
2Adaptability or versatility
If separate drivers are used for output and inverted output signals, then both signals can be provided to the pixel, but the driver size increases
Solution Approach 1:
The patent merges the output driver and inverted output driver into a single integrated circuit structure. The first output circuit and second output circuit share common elements including the clock signal input terminal, input signal terminal, and transistor components, thereby reducing the total area occupied by the driver compared to having separate dedicated drivers.
Solution Approach 2:
The driver circuit employs universal design principles where the same clock signal and input signal are used to control both the first output circuit and second output circuit. This multi-functional approach allows the driver to generate both output and inverted output signals without requiring separate independent driver circuits, thus minimizing the driver area.
3Device complexity
If a single driver outputs both output signal and inverted output signal, then driver size is reduced, but the driver must handle multiple signals simultaneously
Solution Approach 1:
The driver circuit is segmented into distinct functional blocks: a first output circuit for generating the output signal and a second output circuit for generating the inverted output signal. Each circuit has dedicated transistors and connection paths, allowing independent control and simplifying the operation of signal generation while maintaining a compact integrated structure.
Solution Approach 2:
The driver utilizes dynamic control through clock signals to manage the operation of both output circuits. The clock signal dynamically controls the timing and activation of transistors in both the first and second output circuits, enabling coordinated operation of multiple signal outputs without requiring complex static control logic, thus maintaining ease of operation.
Data Source
AI summary
At least one stage of a driver includes a first input circuit that transfers an input signal to a first node in response to a clock signal, a second input circuit that transfers an inverted input signal inverted from the input signal to a second node in response to the clock signal, a first output circuit that outputs a low gate voltage as an output signal in response to a voltage of the first node, and that outputs a high gate voltage as the output signal in response to a voltage of the second node, and a second output circuit that outputs the high gate voltage as an inverted output signal inverted from the output signal in response to the voltage of the first node, and that outputs the low gate voltage as the inverted output signal in response to the voltage of the second node.